Byoung Hun Lee

Orcid: 0000-0002-4540-7731

According to our database1, Byoung Hun Lee authored at least 10 papers between 2004 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2021
Drastic reliability improvement using H2O2/UV treatment of HfO2 for heterogeneous integration.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

2020
Extreme Low Power Technology using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction.
Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020

2019
Demonstration of ternary devices and circuits using dual channel graphene barristors.
Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

2018
Reliability characteristics of MIM capacitor studied with ΔC-F characteristics.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

2016
Design of Ratioless Ternary Inverter Using Graphene Barristor.
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

2015
Neuromorphic Hardware System for Visual Pattern Recognition With Memristor Array and CMOS Neuron.
IEEE Trans. Ind. Electron., 2015

Metal Decoration Effects on the Gas-Sensing Properties of 2D Hybrid-Structures on Flexible Substrates.
Sensors, 2015

2007
Electrical characterization and analysis techniques for the high-kappa era.
Microelectron. Reliab., 2007

2005
Probing stress effects in HfO<sub>2</sub> gate stacks with time dependent measurements.
Microelectron. Reliab., 2005

2004
Effect of Pre-Existing Defects on Reliability Assessment of High-K Gate Dielectrics.
Microelectron. Reliab., 2004


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