Bo-Qian Jiang

According to our database, Bo-Qian Jiang authored at least 4 papers between 2011 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2014

A 0.9- to 8-GHz VCO With a Differential Active Inductor for Multistandard Wireline SerDes.

Kuo-Hsing Cheng, Cheng-Liang Hung, Cihun-Siyong Alex Gong, Jen-Chieh Liu, Bo-Qian Jiang, Shi-Yang Sun

IEEE Trans. Circuits Syst. II Express Briefs, 2014

2012

An All-Digital Clock Synchronization Buffer With One Cycle Dynamic Synchronizing.

Kuo-Hsing Cheng, Kai-Wei Hong, Chi-Fa Hsu, Bo-Qian Jiang

IEEE Trans. Very Large Scale Integr. Syst., 2012

A 6-Gb/s 3X-oversampling-like clock and data recovery in 0.13-µm CMOS technology.

Bo-Qian Jiang, Cheng-Liang Hung, Bing-Hung Chen, Kuo-Hsing Cheng

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011

A 0.06-psRMS SSC-induced jitter, ΔΣ-dithering-free, 6-GHz spread-spectrum clock generator for serial-ATA generation.

Cheng-Liang Hung, Kuo-Hsing Cheng, Yu-Chen Lin, Bo-Qian Jiang, Che-hao Fan, Chi-Yang Chang

Proceedings of the 37th European Solid-State Circuits Conference, 2011