Avik Bose

Orcid: 0000-0002-4592-4632

According to our database1, Avik Bose authored at least 7 papers between 2014 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2021
Dynamic application mapping on CTH network: a performance-centric approach.
Proceedings of the SenSys '21: The 19th ACM Conference on Embedded Networked Sensor Systems, Coimbra, Portugal, November 15, 2021

A scalable NoC topology targeting network performance.
Proceedings of the NoCArc '21: Proceedings of the 14th International Workshop on Network on Chip Architectures, Virtual Event, Greece, October 18, 2021

2020
A low latency energy efficient BFT based 3D NoC design with zone based routing strategy.
J. Syst. Archit., 2020

A cube-tree hybrid NoC topology with 3D mirroring technique for load balancing.
Proceedings of the NanoCoCoA@SenSys '20: Proceedings of the 1st ACM International Workshop on Nanoscale Computing, 2020

Switching at flit level: A Congestion Efficient Flow Control Strategy for Network-on-Chip.
Proceedings of the 28th Euromicro International Conference on Parallel, 2020

2016
STA: A Highly Scalable Low Latency Butterfly Fat Tree Based 3D NoC Design.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

2014
A Low Latency Scalable 3D NoC Using BFT Topology with Table Based Uniform Routing.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014


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