Arunachalam Venkatesan

Orcid: 0000-0002-7797-4749

According to our database1, Arunachalam Venkatesan authored at least 9 papers between 2011 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Hand-held GPU accelerated device for multiclass classification of X-ray images using CNN model.
Microprocess. Microsystems, 2024

2023
Design of high performance and energy efficient convolution array for convolution neural network-based image inference engine.
Eng. Appl. Artif. Intell., November, 2023

Analysis of Optimum 3-Dimensional Array and Fast Data Movement for Efficient Memory Computation in Convolutional Neural Network Models.
Proceedings of the Computer, Communication, and Signal Processing. AI, Knowledge Engineering and IoT for Smart Systems, 2023

2022
Analysis & Design of Convolution Operator for High Speed and High Accuracy Convolutional Neural Network-Based Inference Engines.
IEEE Trans. Computers, 2022

2021
An integrated feature frame work for automated segmentation of COVID-19 infection from lung CT images.
Int. J. Imaging Syst. Technol., 2021

Performance Improvement of Vector-Radix Decimation-in-Frequency 3D-DCT/IDCT Using Variable Word Length.
Circuits Syst. Signal Process., 2021

2018
Efficient dual-precision floating-point fused-multiply-add architecture.
Microprocess. Microsystems, 2018

2014
Efficient VLSI implementation of FFT for orthogonal frequency division multiplexing applications.
IET Circuits Devices Syst., 2014

2011
FPGA implementation & comparison of current trends in memory scheduler for multimedia application.
Proceedings of the ICWET '11 International Conference & Workshop on Emerging Trends in Technology, Mumbai, Maharashtra, India, February 25, 2011


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