Andrew E. Caldwell

According to our database1, Andrew E. Caldwell authored at least 17 papers between 1999 and 2004.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2004
Effective iterative techniques for fingerprinting design IP.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

2003
Hierarchical whitespace allocation in top-down placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

2002
Toward CAD-IP Reuse: A Web Bookshelf of Fundamental Algorithms.
IEEE Des. Test Comput., 2002

2000
Iterative Partitioning with Varying Node Weights.
VLSI Design, 2000

Optimal partitioners and end-case placers for standard-cell layout.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Hypergraph partitioning with fixed vertices [VLSI CAD].
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Design and Implementation of Move-Based Heuristics for VLSI Hypergraph Partitioning.
ACM J. Exp. Algorithmics, 2000

Admissibility Proofs for the LCS* Algorithm.
Proceedings of the Advances in Artificial Intelligence, 2000

Can recursive bisection alone produce routable placements?
Proceedings of the 37th Conference on Design Automation, 2000

GTX: the MARCO GSRC technology extrapolation system.
Proceedings of the 37th Conference on Design Automation, 2000

Improved algorithms for hypergraph bipartitioning.
Proceedings of ASP-DAC 2000, 2000

1999
Analytical Engines are Unnecessary in Top-down Partitioning-based Placement.
VLSI Design, 1999

On wirelength estimations for row-based placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Partitioning with terminals: a "new" problem and new benchmarks.
Proceedings of the 1999 International Symposium on Physical Design, 1999

Hypergraph Partitioning with Fixed Vertices.
Proceedings of the 36th Conference on Design Automation, 1999

Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting.
Proceedings of the 36th Conference on Design Automation, 1999

Design and Implementation of the Fiduccia-Mattheyses Heuristic for VLSI Netlist Partitioning.
Proceedings of the Algorithm Engineering and Experimentation, 1999


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