Andreas Baenisch

According to our database¹, Andreas Baenisch authored at least 8 papers between 2014 and 2018.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

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2018

A flexible mixed-signal image processing pipeline using 3D chip stacks.

[BibT_eX]

[DOI]

J. Real Time Image Process., 2018

2015

Concept for a CMOS Image Sensor Suited for Analog Image Pre-Processing.

[BibT_eX]

[DOI]

CoRR, 2015

A CMOS image sensor with analog pre-processing capability suitable for smart camera applications.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Symposium on Intelligent Signal Processing and Communication Systems, 2015

Implementation of a high-speed flash ADC for high-performance pipeline ADCs in an 180nm CMOS process.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Symposium on Intelligent Signal Processing and Communication Systems, 2015

A low noise amplifier chain for digital satellite radio applications.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Analog computation methods with the help of analog and pseudo-digital carry signals.

[BibT_eX]

[DOI]

Proceedings of the European Conference on Circuit Theory and Design, 2015

Novel control methods for phase lock loops.

[BibT_eX]

[DOI]

Proceedings of the European Conference on Circuit Theory and Design, 2015

2014

A 20-Gbps low jitter analog clock recovery circuit for ultra-wide band Radio systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Andreas Baenisch

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