Alexander Fell

According to our database, Alexander Fell authored at least 20 papers between 2008 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

The MareNostrum Experimental Exascale Platform (MEEP).

Alexander Fell, Daniel J. Mazure, Teresa C. Garcia, Borja Pérez, Xavier Teruel, Pete Wilson, John D. Davis

Supercomput. Front. Innov., 2021

XDIVINSA: eXtended DIVersifying INStruction Agent to Mitigate Power Side-Channel Leakage.

Thinh Hung Pham, Ben Marshall, Alexander Fell, Siew-Kei Lam, Daniel Page

IACR Cryptol. ePrint Arch., 2021

Coyote: An Open Source Simulation Tool to Enable RISC- V in HPC.

Boria Pérez, Alexander Fell, John D. Davis

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Symmetric $k$-Means for Deep Neural Network Compression and Hardware Acceleration on FPGAs.

Akshay Jain, Pulkit Goel, Shivam Aggarwal, Alexander Fell, Saket Anand

IEEE J. Sel. Top. Signal Process., 2020

2019

TAD: time side-channel attack defense of obfuscated source code.

Alexander Fell, Thinh Hung Pham, Siew-Kei Lam

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

CIDPro: Custom Instructions for Dynamic Program Diversification.

Thinh Hung Pham, Alexander Fell, Arnab Kumar Biswas, Siew-Kei Lam, Nandeesha Veeranna

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017

DFGenTool: A Dataflow Graph Generation Tool for Coarse Grain Reconfigurable Architectures.

Manideepa Mukherjee, Alexander Fell, Apala Guha

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Asynchronous 1R-1W dual-port SRAM by using single-port SRAM in 28nm UTBB-FDSOI technology.

Harsh Rawat, K. Bharath, Alexander Fell

Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Automated, inter-macro channel space adjustment and optimization for faster design closure.

Praveen Kumar, Alexander Fell, Sachin Mathur

Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

A Parallel Architecture for High Frame Rate Stereo using Semi-Global Matching.

Akshay Jain, Alexander Fell, Saket Anand

Proceedings of the British Machine Vision Conference 2017, 2017

2015

Floorplan and congestion aware framework for optimal SRAM selection for memory subsystems.

Gaurav Narang, Alexander Fell, Prakhar Raj Gupta, Anuj Grover

Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

A 6T SRAM cell based pipelined 2R/1W memory design using 28nm UTBB-FDSOI.

Ramandeep Kaur, Alexander Fell, Harsh Rawat

Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

A deterministic, minimal routing algorithm for a toroidal, rectangular honeycomb topology using a 2-tupled relative address.

Alexander Fell, S. K. Nandy, Ranjani Narayan

Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

2014

Force-directed scheduling for Data Flow Graph mapping on Coarse-Grained Reconfigurable Architectures.

Alexander Fell, Zoltán Endre Rákossy, Anupam Chattopadhyay

Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

2009

REDEFINE: Runtime reconfigurable polymorphic ASIC.

Mythri Alle, Keshavan Varadarajan, Alexander Fell, C. Ramesh Reddy, Joseph Nimmy, Saptarsi Das, Prasenjit Biswas, Jugantor Chetia, Adarsha Rao, S. K. Nandy, Ranjani Narayan

ACM Trans. Embed. Comput. Syst., 2009

Generic routing rules and a scalable access enhancement for the Network-on-Chip RECONNECT.

Alexander Fell, Prasenjit Biswas, Jugantor Chetia, S. K. Nandy, Ranjani Narayan

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Streaming FFT on REDEFINE-v2: an application-architecture design space exploration.

Alexander Fell, Mythri Alle, Keshavan Varadarajan, Prasenjit Biswas, Saptarsi Das, Jugantor Chetia, S. K. Nandy, Ranjani Narayan

Proceedings of the 2009 International Conference on Compilers, 2009

Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures.

Mythri Alle, Keshavan Varadarajan, Alexander Fell, S. K. Nandy, Ranjani Narayan

Proceedings of the Reconfigurable Computing: Architectures, 2009

2008

RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router.

Joseph Nimmy, C. Ramesh Reddy, Keshavan Varadarajan, Mythri Alle, Alexander Fell, S. K. Nandy, Ranjani Narayan

Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

Synthesis of application accelerators on Runtime Reconfigurable Hardware.

Mythri Alle, Keshavan Varadarajan, Ramesh C. Ramesh, Joseph Nimmy, Alexander Fell, Adarsha Rao, S. K. Nandy, Ranjani Narayan

Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008