Advait Madhavan

Orcid: 0000-0002-4121-1336

According to our database1, Advait Madhavan authored at least 26 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Layer Ensemble Averaging for Improving Memristor-Based Artificial Neural Network Performance.
CoRR, 2024

Energy Efficient Convolutions with Temporal Arithmetic.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023
Programmable electrical coupling between stochastic magnetic tunnel junctions.
CoRR, 2023

Experimental demonstration of a robust training method for strongly defective neuromorphic hardware.
CoRR, 2023

2022
Associative memories using complex-valued Hopfield networks based on spin-torque oscillator arrays.
Neuromorph. Comput. Eng., 2022

2021
Temporal Computing With Superconductors.
IEEE Micro, 2021

Temporal State Machines: Using Temporal Memory to Stitch Time-based Graph Computations.
ACM J. Emerg. Technol. Comput. Syst., 2021

Implementation of a Binary Neural Network on a Passive Array of Magnetic Tunnel Junctions.
CoRR, 2021

Mutual control of stochastic switching for two electrically coupled superparamagnetic tunnel junctions.
CoRR, 2021

In-sensor classification with boosted race trees.
Commun. ACM, 2021

A System for Validating Resistive Neural Network Prototypes.
Proceedings of the ICONS 2021: International Conference on Neuromorphic Systems 2021, 2021

2020
Temporal Memory with Magnetic Racetracks.
CoRR, 2020

Storing and Retrieving Wavefronts with Resistive Temporal Memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020


A Computational Temporal Logic for Superconducting Accelerators.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019
Energy-efficient stochastic computing with superparamagnetic tunnel junctions.
CoRR, 2019

Streaming Batch Eigenupdates for Hardware Neuromorphic Networks.
CoRR, 2019

Boosted Race Trees for Low Energy Classification.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

2018
High-Throughput Pattern Matching With CMOL FPGA Circuits: Case for Logic-in-Memory Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2018

2017
A 4-mm<sup>2</sup> 180-nm-CMOS 15-Giga-cell-updates-per-second DNA sequence alignment engine based on asynchronous race conditions.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
Abusing Hardware Race Conditions for High Throughput Energy Efficient Computation.
PhD thesis, 2016

Energy efficient computation with asynchronous races.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Race Logic: Abusing Hardware Race Conditions to Perform Useful Computation.
IEEE Micro, 2015

A configurable CMOS memory platform for 3D-integrated memristors.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
Race Logic: A hardware acceleration for dynamic programming algorithms.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

2012
Mapping of image and network processing tasks on high-throughput CMOL FPGA circuits.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012


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