Zsolt Tokei
Orcid: 0000-0003-3545-3424
According to our database1,
Zsolt Tokei
authored at least 37 papers
between 2005 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2024
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2024
Mitigating Line-Break Defectivity with a Sandwiched TiN or W Layer for Metal Pitch 18 NM Aspect Ratio 6 Semi-Damascene Interconnects.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
2023
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Emerging Interconnect Exploration for SRAM Application Using Nonconventional H-Tree and Center-Pin Access.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
Towards accurate temperature prediction in BEOL for reliability assessment (Invited).
Proceedings of the IEEE International Reliability Physics Symposium, 2023
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
Electromigration-aware design technology co-optimization for SRAM in advanced technology nodes.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
First demonstration of Two Metal Level Semi-damascene Interconnects with Fully Self-aligned Vias at 18MP.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Logic Scaling Options for the Next 10 Years: From FinFet to CFET, from Dual Damascene to Semi Damascene.
Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022
2021
Proceedings of the IEEE International Reliability Physics Symposium, 2021
Proceedings of the IEEE International Reliability Physics Symposium, 2021
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021
2020
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
2019
Low-Frequency Noise Measurements to Characterize Cu-Electromigration Down to 44nm Metal Pitch.
Proceedings of the IEEE International Reliability Physics Symposium, 2019
2018
Proceedings of the IEEE International Reliability Physics Symposium, 2018
Proceedings of the IEEE International Reliability Physics Symposium, 2018
The first observation of p-type electromigration failure in full ruthenium interconnects.
Proceedings of the IEEE International Reliability Physics Symposium, 2018
2017
Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Impact of via density and passivation thickness on the mechanical integrity of advanced Back-End-Of-Line interconnects.
Microelectron. Reliab., 2017
2016
Design considerations for the mechanical integrity of airgaps in nano-interconnects under chip-package interaction; a numerical investigation.
Microelectron. Reliab., 2016
Evaluation of via density and low-k Young's modulus influence on mechanical performance of advanced node multi-level Back-End-Of-Line.
Microelectron. Reliab., 2016
2015
Technology/circuit co-optimization and benchmarking for graphene interconnects at Sub-10nm technology node.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Proceedings of the IEEE International Reliability Physics Symposium, 2015
Proceedings of the IEEE International Reliability Physics Symposium, 2015
Proceedings of the IEEE International Reliability Physics Symposium, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
Microelectron. Reliab., 2014
As-grown donor-like traps in low-k dielectrics and their impact on intrinsic TDDB reliability.
Microelectron. Reliab., 2014
Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies.
Proceedings of the 44th European Solid State Device Research Conference, 2014
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2008
Study of copper drift during TDDB of intermetal dielectrics by using fully passivated MOS capacitors as test vehicle.
Microelectron. Reliab., 2008
A tool flow for predicting system level timing failures due to interconnect reliability degradation.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
2006
Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system design.
Proceedings of the IFIP VLSI-SoC 2006, 2006
2005
Microelectron. Reliab., 2005
Layout dependency induced deviation from Poisson area scaling in BEOL dielectric reliability.
Microelectron. Reliab., 2005