Ziyad Hanna

According to our database, Ziyad Hanna authored at least 30 papers between 2001 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2015

Democratization of Formal Verification with Collective Intelligence.

Ziyad Hanna

Proceedings of the Formal Methods in Computer-Aided Design, 2015

2014

Challenging problems in industrial formal verification.

Ziyad Hanna

Proceedings of the Formal Methods in Computer-Aided Design, 2014

2012

Formal Analysis of Security Data Paths in RTL Design.

Jamil Mazzawi, Ziyad Hanna

Proceedings of the Hardware and Software: Verification and Testing, 2012

2011

A symbolic execution framework for algorithm-level modelling and verification of computer microarchitecture.

Ziyad Hanna

PhD thesis, 2011

2009

A symbolic execution framework for algorithm-level modelling.

Ziyad Hanna, Thomas F. Melham

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009

2007

Towards a Better Understanding of the Functionality of a Conflict-Driven SAT Solver.

Nachum Dershowitz, Ziyad Hanna, Alexander Nadel

Proceedings of the Theory and Applications of Satisfiability Testing, 2007

Industrial Strength SAT-based Alignability Algorithm for Hardware Equivalence Verification.

Daher Kaiss, Marcelo Skaba, Ziyad Hanna, Zurab Khasidashvili

Proceedings of the Formal Methods in Computer-Aided Design, 7th International Conference, 2007

Abstract Modeling and Formal Verification of Microprocessors.

Ziyad Hanna

Proceedings of the Computer Science, 2007

A Lazy and Layered SMT($\mathcal{BV}$) Solver for Hard Industrial Verification Problems.

Roberto Bruttomesso, Alessandro Cimatti, Anders Franzén, Alberto Griggio, Ziyad Hanna, Alexander Nadel, Amit Palti, Roberto Sebastiani

Proceedings of the Computer Aided Verification, 19th International Conference, 2007

An Efficient Diagnostic Test Pattern Generation Framework Using Boolean Satisfiability.

Feijun Zheng, Kwang-Ting Cheng, Xiaolang Yan, John Moondanos, Ziyad Hanna

Proceedings of the 16th Asian Test Symposium, 2007

2006

A Scalable Algorithm for Minimal Unsatisfiable Core Extraction.

Nachum Dershowitz, Ziyad Hanna, Alexander Nadel

Proceedings of the Theory and Applications of Satisfiability Testing, 2006

Post-reboot Equivalence and Compositional Verification of Hardware.

Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna

Proceedings of the Formal Methods in Computer-Aided Design, 6th International Conference, 2006

Generation of shorter sequences for high resolution error diagnosis using sequential SAT.

Sung-Jui (Song-Ra) Pan, Kwang-Ting Cheng, John Moondanos, Ziyad Hanna

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Encoding RTL Constructs for MathSAT: a Preliminary Report.

Marco Bozzano, Roberto Bruttomesso, Alessandro Cimatti, Anders Franzén, Ziyad Hanna, Zurab Khasidashvili, Amit Palti, Roberto Sebastiani

Proceedings of the Third Workshop on Pragmatics of Decision Procedures in Automated Reasoning, 2005

A Clause-Based Heuristic for SAT Solvers.

Nachum Dershowitz, Ziyad Hanna, Alexander Nadel

Proceedings of the Theory and Applications of Satisfiability Testing, 2005

Bounded Model Checking with QBF.

Nachum Dershowitz, Ziyad Hanna, Jacob Katz

Proceedings of the Theory and Applications of Satisfiability Testing, 2005

Simultaneous SAT-Based Model Checking of Safety Properties.

Zurab Khasidashvili, Alexander Nadel, Amit Palti, Ziyad Hanna

Proceedings of the Hardware and Software Verification and Testing, 2005

Space-Efficient Bounded Model Checking.

Jacob Katz, Ziyad Hanna, Nachum Dershowitz

Proceedings of the 2005 Design, 2005

2004

A Signal Correlation Guided Circuit-SAT Solver.

Feng Lu, Li-C. Wang, Kwang-Ting (Tim) Cheng, John Moondanos, Ziyad Hanna

J. Univers. Comput. Sci., 2004

Parallel Multithreaded Satisfiability Solver: Design and Implementation.

Yulik Feldman, Nachum Dershowitz, Ziyad Hanna

Proceedings of the 3rd International Workshop on Parallel and Distributed Methods in Verification, 2004

Theoretical framework for compositional sequential hardware equivalence verification in presence of design constraints.

Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

2003

Design automation with mixtures of proof strategies for propositional logic.

Gunnar Andersson, Per Bjesse, Byron Cook, Ziyad Hanna

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

SAT-based methods for sequential hardware equivalence verification without synchronization.

Zurab Khasidashvili, Ziyad Hanna

Proceedings of the First International Workshop on Bounded Model Checking, 2003

A signal correlation guided ATPG solver and its applications for solving difficult industrial cases.

Feng Lu, Li-C. Wang, Kwang-Ting Cheng, John Moondanos, Ziyad Hanna

Proceedings of the 40th Design Automation Conference, 2003

2002

High capacity and automatic functional extraction tool for industrial VLSI circuit designs.

Sasha Novakovsky, Shy Shyman, Ziyad Hanna

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Alignability equivalence of synchronous sequential circuits.

Amnon Rosenmann, Ziyad Hanna

Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

TRANS: efficient sequential verification of loop-free circuits.

Zurab Khasidashvili, John Moondanos, Ziyad Hanna

Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

A proof engine approach to solving combinational design automation problems.

Gunnar Andersson, Per Bjesse, Byron Cook, Ziyad Hanna

Proceedings of the 39th Design Automation Conference, 2002

2001

An enhanced cut-points algorithm in formal equivalence verification.

Zurab Khasidashvili, John Moondanos, Daher Kaiss, Ziyad Hanna

Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination.

John Moondanos, Carl-Johan H. Seger, Ziyad Hanna, Daher Kaiss

Proceedings of the Computer Aided Verification, 13th International Conference, 2001