Ziran Zhu
Orcid: 0000-0002-9475-6364
According to our database1,
Ziran Zhu
authored at least 36 papers
between 2017 and 2025.
Collaborative distances:
Collaborative distances:
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Bibliography
2025
Two stage Ordered Escape Routing combined with LP and heuristic algorithm for large scaled PCB.
Integr., 2025
2024
J. Supercomput., November, 2024
LAMPlace: Legalization-Aided Reinforcement Learning-Based Macro Placement for Mixed-Size Designs With Preplaced Blocks.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2024
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
High-Performance Placement Engine for Modern Large-Scale FPGAs With Heterogeneity and Clock Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2024
An Effective Routing Refinement Algorithm Based on Incremental Replacement and Rerouting.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024
An effective routability-driven packing algorithm for large-scale heterogeneous FPGAs.
Integr., January, 2024
Integr., 2024
Proceedings of the IEEE International Conference on Multimedia and Expo, 2024
Proceedings of the Twelfth International Conference on Learning Representations, 2024
Late Breaking Results: Routability-Driven FPGA Macro Placement Considering Complex Cascade Shape and Region Constraints.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
2023
Proceedings of the 15th International Conference on Machine Learning and Computing, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
A Robust Global Routing Engine with High-Accuracy Cell Movement under Advanced Constraints.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
High-performance placement for large-scale heterogeneous FPGAs with clock constraints.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Voronoi Diagram Based Heterogeneous Circuit Layout Centerline Extraction for Mask Verification.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2021
A Robust Modulus-Based Matrix Splitting Iteration Method for Mixed-Cell-Height Circuit Legalization.
ACM Trans. Design Autom. Electr. Syst., 2021
Topology-Aware Bus Routing in Complex Networks of Very-Large-Scale Integration with Nonuniform Track Configurations and Obstacles.
Complex., 2021
Late Breaking Results: Heterogeneous Circuit Layout Centerline Extraction for Mask Verification.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Late Breaking Results: An Effective Legalization Algorithm for Heterogeneous FPGAs with Complex Constraints.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Mixed-cell-height legalization considering complex minimum width constraints and half-row fragmentation effect.
Integr., 2020
An Improved Simulated Annealing Algorithm With Excessive Length Penalty for Fixed-Outline Floorplanning.
IEEE Access, 2020
Hamiltonian Path Based Mixed-Cell-Height Legalization for Neighbor Diffusion Effect Mitigation.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2018
Proceedings of the International Conference on Computer-Aided Design, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
IEEE Trans. Computers, 2017
An adaptive hybrid memetic algorithm for thermal-aware non-slicing VLSI floorplanning.
Integr., 2017
Proceedings of the 54th Annual Design Automation Conference, 2017