Zipeng Chen
Orcid: 0009-0002-5064-0834
According to our database1,
Zipeng Chen
authored at least 31 papers
between 2016 and 2024.
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Bibliography
2024
Evaluating Performance of Different RNA Secondary Structure Prediction Programs Using Self-cleaving Ribozymes.
Genom. Proteom. Bioinform., 2024
Cross Layer Weakly Supervised Data Augmentation Network for Offline Signature Verification.
Proceedings of the International Joint Conference on Neural Networks, 2024
2023
Parametric design and modeling method of carbon fiber reinforcement plastic-laminated components applicable for multi-material vehicle body development.
J. Comput. Des. Eng., December, 2023
IEEE J. Solid State Circuits, February, 2023
IEEE ACM Trans. Audio Speech Lang. Process., 2023
Proceedings of the Pattern Recognition and Computer Vision - 6th Chinese Conference, 2023
Dynamic Recommendation System Based on Event Knowledge Graph in Telecom O&M (Telecom Operations and Maintenance Field).
Proceedings of the 7th International Conference on Computer Science and Application Engineering, 2023
2022
Difference-Guided Representation Learning Network for Multivariate Time-Series Classification.
IEEE Trans. Cybern., 2022
A Self-Adapted Two-Point Modulation Type-II Digital PLL for Fast Chirp Rate and Wide Chirp-Bandwidth FMCW Signal Generation.
IEEE J. Solid State Circuits, 2022
Sci. China Inf. Sci., 2022
Research on the Application of LSTM Model Based on Electrical Equipment in Electromagnetic Field Calculation.
Proceedings of the International Conference on Artificial Intelligence, 2022
2021
IEEE ACM Trans. Audio Speech Lang. Process., 2021
Sci. China Inf. Sci., 2021
A 122-168GHz Radar/Communication Fusion-Mode Transceiver with 30GHz Chirp Bandwidth, 13dBm Psat, and 8.3dBm OP1dB in 28nm CMOS.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
A 11.1-to-14.2 GHz Self-adapted Two-point Modulation Dual-path Type-II Digital PLL Concurrently Achieving 124.7-MHz/μs Chirp Rate and 2.27-GHz Bandwidth.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Proceedings of the Thirtieth International Joint Conference on Artificial Intelligence, 2021
Proceedings of the 59th Annual Meeting of the Association for Computational Linguistics and the 11th International Joint Conference on Natural Language Processing, 2021
2020
A 77-GHz Mixed-Mode FMCW Generator Based on a Vernier TDC With Dual Rising-Edge Fractional-Phase Detector.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
A U-Band PLL Using Implicit Distributed Resonators for Sub-THz Wireless Transceivers in 40 nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Microelectron. J., 2020
A CMOS 76-81-GHz 2-TX 3-RX FMCW Radar Transceiver Based on Mixed-Mode PLL Chirp Generator.
IEEE J. Solid State Circuits, 2020
A Fully Integrated K-Band Dual Down-Conversion Receiver for Radar Applications in 90 nm CMOS.
IEEE Access, 2020
A 44-52 GHz Reflection-type Phase Shifter with 1.4° Phase Resolution in 28nm CMOS Process.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020
MODE-LSTM: A Parameter-efficient Recurrent Network with Multi-Scale for Sentence Classification.
Proceedings of the 2020 Conference on Empirical Methods in Natural Language Processing, 2020
2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A Fully Integrated 27.5-30.5 GHz 8-Element Phased-Array Transmit Front-end Module in 65 nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
A 0.1-5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS.
Microelectron. J., 2018
A 77-GHz Mixed-Mode FMCW Generator Based on a Vernier TDC with Dual Rising-Edge Fractional-Phase Detector.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
A CMOS 76-81 GHz 2TX 3RX FMCW Radar Transceiver Based on Mixed-Mode PLL Chirp Generator.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
An Interference-Robust Reconfigurable Receiver With Automatic Frequency-Calibrated LNA in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2017
2016
A reconfigurable IF receiver supporting intra-band non-contiguous carrier aggregation in 65 nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016