Zihao Xuan

Orcid: 0000-0002-4573-4556

According to our database1, Zihao Xuan authored at least 9 papers between 2021 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

2021
2022
2023
2024
2025
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3
4
5
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Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2025
A dynamic decoder with speculative termination for low latency inference in spiking neural networks.
Neurocomputing, 2025

2024
TQ-TTFS: High-Accuracy and Energy-Efficient Spiking Neural Networks Using Temporal Quantization Time-to-First-Spike Neuron.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023
A Brain-Inspired ADC-Free SRAM-Based In-Memory Computing Macro With High-Precision MAC for AI Application.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2023

AiDAC: A Low-Cost In-Memory Computing Architecture with All-Analog Multi-Bit Compute and Interconnect.
CoRR, 2023

An 1.38nJ/Inference Clock-Free Mixed-Signal Neuromorphic Architecture Using ReL-PSP Function and Computing-in-Memory.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023

A 28nm 15.09nJ/inference Neuromorphic Processor with SRAM-Based Charge Domain in-Memory-Computing.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022
High-Efficiency Data Conversion Interface for Reconfigurable Function-in-Memory Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2022

HPSW-CIM: A Novel ReRAM-Based Computing-in-Memory Architecture with Constant-Term Circuit for Full Parallel Hybrid-Precision-Signed-Weight MAC Operation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
A 40-nm 202.3nJ/Classification Neuromorphic Architecture Employing In-SRAM Charge-Domain Compute.
Proceedings of the 14th IEEE International Conference on ASIC, 2021


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