Zichu Qi

According to our database1, Zichu Qi authored at least 10 papers between 2005 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
A scan chain optimization method for diagnosis.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

2013
Godson-3B1500: A 32nm 1.35GHz 40W 172.8GFLOPS 8-core processor.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2011
Design for Testability Features of Godson-3 Multicore Microprocessor.
J. Comput. Sci. Technol., 2011

Godson-3B: A 1GHz 40W 8-core 128GFLOPS processor in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
Design of Low-Cost High-Performance Floating-Point Fused Multiply-Add with Reduced Power.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

2009
A case study of improving at-speed testing coverage of a gigahertz microprocessor.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

A Scalable Scan Architecture for Godson-3 Multicore Microprocessor.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
Testing content addressable memories using instructions and march-like algorithms.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2006
Parallel Error Detection for Leading Zero Anticipation.
J. Comput. Sci. Technol., 2006

2005
A novel design of leading zero anticipation circuit with parallel error detection.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005


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