Zibin Dai
Orcid: 0000-0003-0359-8434
According to our database1,
Zibin Dai
authored at least 26 papers
between 2007 and 2024.
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Bibliography
2024
RGMU: A High-flexibility and Low-cost Reconfigurable Galois Field Multiplication Unit Design Approach for CGRCA.
ACM Trans. Design Autom. Electr. Syst., March, 2024
2023
R/B-SecArch: A strong isolated SoC architecture based on red/black concept for secure and efficient cryptographic services.
Microelectron. J., December, 2023
CBDC-PUF: A Novel Physical Unclonable Function Design Framework Utilizing Configurable Butterfly Delay Chain Against Modeling Attack.
ACM Trans. Design Autom. Electr. Syst., September, 2023
Extending the classical side-channel analysis framework to access-driven cache attacks.
Comput. Secur., June, 2023
MA-GRNN:a high-efficient modeling attack approach utilizing generalized regression neural network for XOR arbiter physical unclonable functions.
IEICE Electron. Express, 2023
2022
A Low-Overhead and High-Security Cryptographic Circuit Design Utilizing the TIGFET-Based Three-Phase Single-Rail Pulse Register against Side-Channel Attacks.
ACM Trans. Design Autom. Electr. Syst., 2022
A Comprehensive Evaluation of Integrated Circuits Side-Channel Resilience Utilizing Three-Independent-Gate Silicon Nanowire Field Effect Transistors-Based Current Mode Logic.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEICE Trans. Inf. Syst., 2022
A Cost-Sensitive Golden Chip-Free Hardware Trojan Detection Using Principal Component Analysis and Naïve Bayes Classification Algorithm.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022
2020
PVHArray: An Energy-Efficient Reconfigurable Cryptographic Logic Array With Intelligent Mapping.
IEEE Trans. Very Large Scale Integr. Syst., 2020
2019
An Efficient ASIC Implementation of Public Key Cryptography Algorithm SM2 Based on Module Arithmetic Logic Unit.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2018
A single-supply sub-threshold level shifter with an internal supply feedback loop for multi-voltage applications.
IEICE Electron. Express, 2018
2017
A highly efficient reconfigurable rotation unit based on an inverse butterfly network.
Frontiers Inf. Technol. Electron. Eng., 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
An area-efficient interconnection network for coarse-grain reconfigurable cryptographic array.
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2015
A High-Throughput Processor for Dual-Field Elliptic Curve Cryptography with Power Analysis Resistance.
Proceedings of the 2015 IEEE 12th Intl Conf on Ubiquitous Intelligence and Computing and 2015 IEEE 12th Intl Conf on Autonomic and Trusted Computing and 2015 IEEE 15th Intl Conf on Scalable Computing and Communications and Its Associated Workshops (UIC-ATC-ScalCom), 2015
Fast Parallel Extract-Shift and Parallel Deposit-Shift in General-Purpose Processors.
Proceedings of the 2015 IEEE 12th Intl Conf on Ubiquitous Intelligence and Computing and 2015 IEEE 12th Intl Conf on Autonomic and Trusted Computing and 2015 IEEE 15th Intl Conf on Scalable Computing and Communications and Its Associated Workshops (UIC-ATC-ScalCom), 2015
Study and implementation of cluster hierarchical memory system of multicore cryptographic processor.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2013
Design and Implementation of Configurable LFSR Instructions Targeted at Stream Cipher Processing.
J. Circuits Syst. Comput., 2013
2011
Research on reconfigurable multiplier unit based on GF[(2<sup>8</sup>)]<sup>4</sup> field of symmetric cryptography.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
2009
The Research of NULL Convention Logic Circuit Computing Model Targeted at Block Cipher Processing.
Proceedings of the Fifth International Conference on Information Assurance and Security, 2009
2008
Proceedings of the PACIIA 2008, 2008
The Research and Implementation of Reconfigurable Processor Architecture for Block Cipher Processing.
Proceedings of the International Conference on Embedded Software and Systems, 2008
2007
Proceedings of the Advanced Parallel Processing Technologies, 7th International Symposium, 2007