Zhuolun He

Orcid: 0009-0009-4909-6588

According to our database¹, Zhuolun He authored at least 28 papers between 2017 and 2025.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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On csauthors.net:

Bibliography

2025

FGNN2: A Powerful Pretraining Framework for Learning the Logic Functionality of Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2025

2024

ChatEDA: A Large Language Model Powered Autonomous Agent for EDA.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024

Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA.

[BibT_eX]

[DOI]

CoRR, 2024

IncreMacro: Incremental Macro Placement Refinement.

[BibT_eX]

[DOI]

Proceedings of the 2024 International Symposium on Physical Design, 2024

Large Language Models for EDA: Future or Mirage?

[BibT_eX]

[DOI]

Zhuolun He

Bei Yu

Proceedings of the 2024 International Symposium on Physical Design, 2024

Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs.

[BibT_eX]

[DOI]

Proceedings of the 2024 International Symposium on Physical Design, 2024

Parameter-Efficient Sparsity Crafting from Dense to Mixture-of-Experts for Instruction Tuning on General Tasks.

[BibT_eX]

[DOI]

Proceedings of the 2024 Conference on Empirical Methods in Natural Language Processing, 2024

CBTune: Contextual Bandit Tuning for Logic Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Lesyn: Placement-aware Logic Resynthesis for Non-Integer Multiple-Cell-Height Designs.

[BibT_eX]

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

PDRC: Package Design Rule Checking via GPU-Accelerated Geometric Intersection Algorithms for Non-Manhattan Geometry.

[BibT_eX]

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

LSTP: A Logic Synthesis Timing Predictor.

[BibT_eX]

[DOI]

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023

Efficient Super-Resolution System With Block-Wise Hybridization and Quantized Winograd on FPGA.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

Efficient Arithmetic Block Identification With Graph Learning and Network-Flow.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

AlphaSyn: Logic Synthesis Optimization with Efficient Monte Carlo Tree Search.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Invited Paper: Heterogeneous Acceleration for Design Rule Checking.

[BibT_eX]

[DOI]

Zhuolun He

Bei Yu

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Efficient Design Rule Checking with GPU Acceleration.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

OpenDRC: An Efficient Open-Source Design Rule Checking Engine with Hierarchical GPU Acceleration.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

AutoGraph: Optimizing DNN Computation Graph for Parallel GPU Kernel Execution.

[BibT_eX]

[DOI]

Proceedings of the Thirty-Seventh AAAI Conference on Artificial Intelligence, 2023

2022

X-Check: CPU-Accelerated Design Rule Checking via Parallel Sweepline Algorithms.

[BibT_eX]

[DOI]

Zhuolun He

Yuzhe Ma

Bei Yu

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Functionality matters in netlist representation learning.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

Graph Learning-Based Arithmetic Block Identification.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Physical Synthesis for Advanced Neural Network Processors.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

Deep Model Compression and Inference Speedup of Sum-Product Networks on Tensor Trains.

[BibT_eX]

[DOI]

IEEE Trans. Neural Networks Learn. Syst., 2020

HOTCAKE: Higher Order Tucker Articulated Kernels for Deeper CNN Compression.

[BibT_eX]

[DOI]

CoRR, 2020

Understanding Graphs in EDA: From Shallow to Deep Learning.

[BibT_eX]

[DOI]

Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

Learn to Floorplan through Acquisition of Effective Local Search Heuristics.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

2018

FPGA-Based Real-Time Super-Resolution System for Ultra High Definition Videos.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

2017

FPGA Acceleration for Computational Glass-Free Displays.

[BibT_eX]

[DOI]

Zhuolun He

Guojie Luo

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

Zhuolun He

Timeline

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