Zhuo Li

IEEE Des. Test, 2020

2018

MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees.

[BibT_eX]

[DOI]

Proceedings of the 2018 International Symposium on Physical Design, 2018

2017

Stitch aware detailed placement for multiple E-beam lithography.

[BibT_eX]

[DOI]

Integr., 2017

2015

Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

2014

Techniques for scalable and effective routability evaluation.

[BibT_eX]

[DOI]

Yaoguang Wei

Cliff C. N. Sze

ACM Trans. Design Autom. Electr. Syst., 2014

Pacman: driving nonuniform clock grid loads for low-skew robust clock network.

[BibT_eX]

[DOI]

Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2014

2013

Structure-Aware Placement Techniques for Designs With Datapaths.

[BibT_eX]

[DOI]

Myung-Chul Kim

Earl E. Swartzlander Jr.

David Z. Pan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Clock power minimization using structured latch templates and decision tree induction.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

ICCAD-2013 CAD contest in placement finishing and benchmark suite.

[BibT_eX]

[DOI]

Myung-Chul Kim

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

The overview of 2013 CAD contest at ICCAD.

[BibT_eX]

[DOI]

Iris Hui-Ru Jiang

Hwei-Tseng Wang

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

ICCAD-2013 CAD contest in mask optimization and benchmark suite.

[BibT_eX]

[DOI]

Shayak Banerjee

Sani R. Nassif

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

CATALYST: planning layer directives for effective design closure.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Routing congestion estimation with real design constraints.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

$O(mn)$ Time Algorithm for Optimal Buffer Insertion of Nets With $m$ Sinks.

[BibT_eX]

[DOI]

Nancy Ying Zhou

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Keep it straight: teaching placement how to better handle designs with datapaths.

[BibT_eX]

[DOI]

Myung-Chul Kim

Earl E. Swartzlander Jr.

David Z. Pan

Proceedings of the International Symposium on Physical Design, 2012

ICCAD-2012 CAD contest in design hierarchy aware routability-driven placement and benchmark suite.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2012 TAU power grid simulation contest: Benchmark suite and results.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Opening: Introduction to CAD contest at ICCAD 2012: CAD contest.

[BibT_eX]

[DOI]

Iris Hui-Ru Jiang

Yih-Lang Li

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Placement: Hot or Not?

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

GLARE: global and local wiring aware routability evaluation.

[BibT_eX]

[DOI]

Yaoguang Wei

Cliff C. N. Sze

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

The DAC 2012 routability-driven placement contest and benchmark suite.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Guiding a physical design closure system to produce easier-to-route designs with more predictable timing.

[BibT_eX]

[DOI]

Nancy Y. Zhou

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Yield estimation via multi-cones.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011

Shedding Physical Synthesis Area Bloat.

[BibT_eX]

[DOI]

VLSI Design, 2011

CAD for Gigascale SoC Design and Verification Solutions.

[BibT_eX]

[DOI]

Yangdong Deng

VLSI Design, 2011

Physical Synthesis with Clock-Network Optimization for Large Systems on Chips.

[BibT_eX]

[DOI]

Gi-Joon Nam

Igor L. Markov

IEEE Micro, 2011

Quantifying academic placer performance on custom designs.

[BibT_eX]

[DOI]

Earl E. Swartzlander Jr.

Proceedings of the 2011 International Symposium on Physical Design, 2011

The ISPD-2011 routability-driven placement contest and benchmark suite.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Symposium on Physical Design, 2011

2011 TAU power grid simulation contest: Benchmark suite and results.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010

ITOP: integrating timing optimization within placement.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Symposium on Physical Design, 2010

Ultra-fast interconnect driven cell cloning for minimizing critical path delay.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Symposium on Physical Design, 2010

What makes a design difficult to route.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Symposium on Physical Design, 2010

New placement prediction and mitigation techniques for local routing congestion.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Detecting tangled logic structures in VLSI netlists.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

2009

A Fully Polynomial-Time Approximation Scheme for Timing-Constrained Minimum Cost Layer Assignment.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2009

The impact of BEOL lithography effects on the SRAM cell performance and yield.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

A faster approximation scheme for timing driven minimum cost layer assignment.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Symposium on Physical Design, 2009

A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

2008

Buffer Insertion Basics.

[BibT_eX]

[DOI]

Jiang Hu

Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A Root-Finding Method for Assessing SRAM Stability.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Fast interconnect synthesis with layer assignment.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Symposium on Physical Design, 2008

SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

Pyramids: an efficient computational geometry-based approach for timing-driven placement.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

A polynomial time approximation scheme for timing constrained minimum cost layer assignment.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Path smoothing via discrete optimization.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

2007

Wire Sizing for Non-Tree Topology.

[BibT_eX]

[DOI]

Nancy Ying Zhou

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Fast Algorithms for Slew-Constrained Minimum Cost Buffering.

[BibT_eX]

[DOI]

Jiang Hu

Shrirang K. Karandikar

Chin Ngai Sze

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Techniques for Fast Physical Synthesis.

[BibT_eX]

[DOI]

Shrirang K. Karandikar

Proc. IEEE, 2007

An O(bn^2) Time Algorithm for Optimal Buffer Insertion with b Buffer Types

[BibT_eX]

[DOI]

CoRR, 2007

The nuts and bolts of physical synthesis.

[BibT_eX]

[DOI]

Shrirang K. Karandikar

Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007

Probabilistic Congestion Prediction with Partial Blockages.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Fast Capacitance Extraction in Multilayer, Conformal and Embedded Dielectric using Hybrid Boundary Element Method.

[BibT_eX]

[DOI]

Nancy Ying Zhou

Proceedings of the 44th Design Automation Conference, 2007

A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

An O(bn2) time algorithm for optimal buffer insertion with b buffer types.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

A new RLC buffer insertion algorithm.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Buffer insertion in large circuits with constructive solution search techniques.

[BibT_eX]

[DOI]

Mandar Waghmode

Proceedings of the 43rd Design Automation Conference, 2006

An O(mn) time algorithm for optimal buffer insertion of nets with m sinks.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Fast interconnect optimization.

[BibT_eX]

[DOI]

PhD thesis, 2005

A fast algorithm for optimal buffer insertion.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Longest-path selection for delay test under process variation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

A More Effective CEFF.

[BibT_eX]

[DOI]

Sani R. Nassif

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Making fast buffer insertion even faster via approximation techniques.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

A Statistical Fault Coverage Metric for Realistic Path Delay Faults.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004

K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

PARADE: PARAmetric Delay Evaluation under Process Variation.

[BibT_eX]

[DOI]

Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

A circuit level fault model for resistive bridges.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2003

A Circuit Level Fault Model for Resistive Opens and Bridges.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Process variation dimension reduction based on SVD.

[BibT_eX]

[DOI]

Xiang Lu

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

CodSim -- A Combined Delay Fault Simulator.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

An O(nlogn) time algorithm for optimal buffer insertion.

[BibT_eX]

[DOI]