Zhufei Chu

Proceedings of the 20th International Conference on Synthesis, 2024

A Semi-Tensor Product based Circuit Simulation for SAT-sweeping.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

FPGA EDA - Design Principles and Implementation

[BibT_eX]

[DOI]

Springer, ISBN: 978-981-99-7754-3, 2024

2023

An efficient circuit-based SAT solver and its application in logic equivalence checking.

[BibT_eX]

[DOI]

Kunmei Hu

Microelectron. J., December, 2023

A Semi-Tensor Product Based All Solutions Boolean Satisfiability Solver.

[BibT_eX]

[DOI]

Hongyang Pan

J. Comput. Sci. Technol., June, 2023

DeepGate2: Functionality-Aware Circuit Representation Learning.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Exact Synthesis Based on Semi-Tensor Product Circuit Solver.

[BibT_eX]

[DOI]

Hongyang Pan

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

2022 roadmap on neuromorphic devices and applications research in China.

[BibT_eX]

[DOI]

Neuromorph. Comput. Eng., December, 2022

Efficient Design of Majority-Logic-Based Approximate Arithmetic Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2022

Logic Synthesis Optimization Sequence Tuning Using RL-Based LSTM and Graph Isomorphism Network.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Stochastic circuit synthesis via satisfiability.

[BibT_eX]

[DOI]

Xiang He

Integr., 2022

The prediction of the quality of results in Logic Synthesis using Transformer and Graph Neural Networks.

[BibT_eX]

[DOI]

Chenghao Yang

CoRR, 2022

2021

BCD Adder Designs Based on Three-Input XOR and Majority Gates.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Defect-Tolerant Mapping of CMOL Circuit Targeting Delay Optimization.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2021

Inversion Optimization Strategy Based on Primitives with Complement Attributes.

[BibT_eX]

[DOI]

Huiming Tian

J. Comput. Sci. Technol., 2021

MinSC: An Exact Synthesis-Based Method for Minimal-Area Stochastic Circuits under Relaxed Error Bound.

[BibT_eX]

[DOI]

Xuan Wang

Weikang Qian

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Design of Majority Logic Based 4-bit Approximate Subtractors and its Application in Divider.

[BibT_eX]

[DOI]

Chuanhe Shang

Proceedings of the 14th IEEE International Conference on ASIC, 2021

An Efficient Demultiplexer Design in Quantum-dot Cellular Automata.

[BibT_eX]

[DOI]

Jianguo Ni

Pierre-Emmanuel Gaillardon

Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020

Advanced Functional Decomposition Using Majority and Its Applications.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A High-Performance Design of Generalized Pipeline Cellular Array.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2020

2019

Through-Silicon Via-Based Capacitor and Its Application in LDO Regulator Design.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

Multi-objective algebraic rewriting in XOR-majority graphs.

[BibT_eX]

[DOI]

Integr., 2019

Exact Synthesis of Boolean Functions in Majority-of-Five Forms.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Structural rewriting in XOR-majority graphs.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Area Optimization of MPRM Circuits Using Approximate Computing.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018

Functional decomposition using majority.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains.

[BibT_eX]

[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016

Multi-supply voltage (MSV) driven SoC floorplanning for fast design convergence.

[BibT_eX]

[DOI]

Integr., 2016

Efficient power pad assignment for multi-voltage SoC and its application in floorplanning.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2016

2014

Efficient nonrectangular shaped voltage island aware floorplanning with nonrandomized searching engine.

[BibT_eX]

[DOI]

Microelectron. J., 2014

Level shifter planning for timing constrained multi-voltage SoC floorplanning.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

2013

Low Power State Assignment Algorithm for FSMs Considering Peak Current Optimization.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2013

Voltage Drop Aware Power Pad Assignment and Floorplanning for Multi-voltage SoC Designs.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Computer-Aided Design and Computer Graphics, 2013

2012

Cell Mapping for Nanohybrid Circuit Architecture Using Genetic Algorithm.

[BibT_eX]

[DOI]