Zhou Jin

Orcid: 0000-0002-0632-9494

Affiliations:

China University of Petroleum, College of Information Science and Engineering, Beijing, China
Waseda University, Research Center, Kitakyushu, Japan (former, PhD 2015)

According to our database¹, Zhou Jin authored at least 38 papers between 2013 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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In proceedings

Article

PhD thesis

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Bibliography

2024

A Parallel Simulation Framework Incorporating Machine Learning-Based Hotspot Detection for Accelerated Power Grid Analysis.

[BibT_eX]

[DOI]

Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024

Cuper: Customized Dataflow and Perceptual Decoding for Sparse Matrix-Vector Multiplication on HBM-Equipped FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Heterogeneous Static Timing Analysis with Advanced Delay Calculator.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

ISPT-Net: A Noval Transient Backward-Stepping Reduction Policy by Irregular Sequential Prediction Transformer.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

TSA-TICER: A Two-Stage TICER Acceleration Framework for Model Order Reduction.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Efficient Spectral-Aware Power Supply Noise Analysis for Low-Power Design Verification.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

MSH: A Multi-Stage HiZ-Aware Homotopy Framework for Nonlinear DC Analysis.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

MAUnet: Multiscale Attention U-Net for Effective IR Drop Prediction.

[BibT_eX]

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

MASC: A Memory-Efficient Adjoint Sensitivity Analysis through Compression Using Novel Spatiotemporal Prediction.

[BibT_eX]

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

ReCG: ReRAM-Accelerated Sparse Conjugate Gradient.

[BibT_eX]

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Unleashing the Potential of AQFP Logic Placement via Entanglement Entropy and Projection.

[BibT_eX]

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Machine Learning and GPU Accelerated Sparse Linear Solvers for Transistor-Level Circuit Simulation: A Perspective Survey (Invited Paper).

[BibT_eX]

[DOI]

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023

OSSP-PTA: An Online Stochastic Stepping Policy for PTA on Reinforcement Learning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

BoA-PTA: A Bayesian Optimization Accelerated PTA Solver for SPICE Simulation.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., March, 2023

Adaptive Stepping PTA for DC Analysis Based on Reinforcement Learning.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2023

PanguLU: A Scalable Regular Two-Dimensional Block-Cyclic Sparse Direct Solver on Distributed Heterogeneous Systems.

[BibT_eX]

[DOI]

Proceedings of the International Conference for High Performance Computing, 2023

Accelerating Sparse LU Factorization with Density-Aware Adaptive Matrix Multiplication for Circuit Simulation.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

AmgR: Algebraic Multigrid Accelerated on ReRAM.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Three Challenges in ReRAM-Based Process-In-Memory for Neural Network.

[BibT_eX]

[DOI]

Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022

TileSpGEMM: a tiled algorithm for parallel sparse general matrix-matrix multiplication on GPUs.

[BibT_eX]

[DOI]

Proceedings of the PPoPP '22: 27th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, Seoul, Republic of Korea, April 2, 2022

A survey and perspective on electronic design automation tools for ensuring SoC security.

[BibT_eX]

[DOI]

Proceedings of the 19th International SoC Design Conference, 2022

TileSpMSpV: A Tiled Algorithm for Sparse Matrix-Sparse Vector Multiplication on GPUs.

[BibT_eX]

[DOI]

Proceedings of the 51st International Conference on Parallel Processing, 2022

Accelerating nonlinear DC circuit simulation with reinforcement learning.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Application of Deep Learning in Back-End Simulation: Challenges and Opportunities.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

Segmented Merge: A New Primitive for Parallel Sparse Matrix Computations.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 2021

BoA-PTA, A Bayesian Optimization Accelerated Error-Free SPICE Solver.

[BibT_eX]

[DOI]

CoRR, 2021

Implementing LU and Cholesky factorizations on artificial intelligence accelerators.

[BibT_eX]

[DOI]

CCF Trans. High Perform. Comput., 2021

TileSpMV: A Tiled Algorithm for Sparse Matrix-Vector Multiplication on GPUs.

[BibT_eX]

[DOI]

Proceedings of the 35th IEEE International Parallel and Distributed Processing Symposium, 2021

PALBBD: A Parallel ArcLength Method Using Bordered Block Diagonal Form for DC Analysis.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

SFLU: Synchronization-Free Sparse LU Factorization for Fast Circuit Simulation on GPUs.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

Two-Phase Multivariate Time Series Clustering to Classify Urban Rail Transit Stations.

[BibT_eX]

[DOI]

IEEE Access, 2020

2018

An adaptive dynamic-element PTA method for solving nonlinear DC operating point of transistor circuits.

[BibT_eX]

[DOI]

Zhou Jin

Meiping Liu

Xiao Wu

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

2017

An Adaptive Time-Step Control Method in Damped Pseudo-Transient Analysis for Solving Nonlinear DC Circuit Equations.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

2015

A netlist implementation of the Newton fixed-point homotopy method for MOS transistor circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

2014

The limitation for the growth of step of DPTA method.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

A ramping method combined with the damped PTA algorithm to find the DC operating points for nonlinear circuits.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

2013

An Effective and Globally Convergent Newton Fixed-Point Homotopy Method for MOS Transistor Circuits.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Effective Implementation and Embedding Algorithms of CEPTA Method for Finding DC Operating Points.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Zhou Jin

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