Zhong-Jian Bian

According to our database, Zhong-Jian Bian authored at least 5 papers between 2021 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Computing in-memory with cascaded spintronic devices for AI edge.

Zhong-Jian Bian, Bo Liu, Hao Cai

Comput. Electr. Eng., August, 2023

A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference.

Hao Cai, Zhong-Jian Bian, Yaoru Hou, Yongliang Zhou, Jia-Le Cui, Yanan Guo, Xiaoyun Tian, Bo Liu, Xin Si, Zhen Wang, Jun Yang, Weiwei Shan

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022

Towards Near LLC Speed STT-MRAM Sensing Using Reconfigurable Clock Trimming.

Xiaoyun Tian, Zhong-Jian Bian, Hao Cai

Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

2021

In-MRAM Computing Elements with Single-Step Convolution and Fully Connected for BNN/TNN.

Zhong-Jian Bian, Yanan Guo, Bo Liu, Hao Cai

Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

Modified Peripheral MRAM Sensing for In-memory Boolean Logic.

Zhong-Jian Bian, Xiaofeng Hong, Juntong Chen, Hao Cai

Proceedings of the 14th IEEE International Conference on ASIC, 2021