Zhiyuan Yang

Orcid: 0000-0002-2250-7959

Affiliations:
  • University of Maryland, Department of Electrical & Computer Engineering, College Park, MD, USA


According to our database1, Zhiyuan Yang authored at least 15 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Bibliography

2024
Exploring the Adversarial Frontier: Quantifying Robustness via Adversarial Hypervolume.
CoRR, 2024

PuriDefense: Randomized Local Implicit Adversarial Purification for Defending Black-box Query-based Attacks.
CoRR, 2024

2020
DRAMsim3: A Cycle-Accurate, Thermal-Capable DRAM Simulator.
IEEE Comput. Archit. Lett., 2020

2019
Enhanced Phase-Driven Q-Learning-Based DRM for Multicore Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

2018
HMCTherm: a cycle-accurate HMC simulator integrated with detailed power and thermal simulation.
Proceedings of the International Symposium on Memory Systems, 2018

Value-driven Synthesis for Neural Network ASICs.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

2017
TSV-Based 3-D ICs: Design Methods and Tools.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Design Space Modeling and Simulation for Physically Constrained 3D CPUs.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Phase-driven Learning-based Dynamic Reliability Management For Multi-core Processors.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Thermoelectric Codesign of 3-D CPUs and Embedded Microfluidic Pin-Fin Heatsinks.
IEEE Des. Test, 2016

Post-Placement Optimization for Thermal-Induced Mechanical Stress Reduction.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Electromigration-aware placement for 3D-ICs.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Voltage Noise Induced DRAM Soft Error Reduction Technique for 3D-CPUs.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Physical Design of 3D FPGAs Embedded with Micro-channel-based Fluidic Cooling.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

ECO Based Placement and Routing Framework for 3D FPGAs with Micro-fluidic Cooling.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016


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