Zhiyuan Liu
Orcid: 0000-0003-0775-9100Affiliations:
- Southeast University, School of Electronic Science and Engineering, National ASIC System Engineering Research Center, Nanjing, China
According to our database1,
Zhiyuan Liu
authored at least 7 papers
between 2019 and 2021.
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Bibliography
2021
Semi-Analytical Path Delay Variation Model With Adjacent Gates Decorrelation for Subthreshold Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
2020
Statistical Timing Model for Subthreshold Circuit with Correlated Variation Consideration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
An Analytical Gate Delay Model in Near/Subthreshold Domain Considering Process Variation.
IEEE Access, 2019
Accurate and Efficient Interdependent Timing Model for Flip-Flop in Wide Voltage Region.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019
A Statistical Timing Model for CMOS Inverter in Near-threshold Region Considering Input Transition Time.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the International Conference on Computer-Aided Design, 2019
A Statistical Current and Delay Model Based on Log-Skew-Normal Distribution for Low Voltage Region.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019