Zhiyong Zhang
Orcid: 0000-0002-8782-2730Affiliations:
- Quan Cheng Laboratory, Jinan, China
- Shandong University, School of Computer Science and Technology, China (PhD 2017)
According to our database1,
Zhiyong Zhang
authored at least 23 papers
between 2012 and 2024.
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Online presence:
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on orcid.org
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Bibliography
2024
ASHL: An Adaptive Multi-Stage Distributed Deep Learning Training Scheme for Heterogeneous Environments.
IEEE Trans. Computers, January, 2024
H2-RAID: Improving the reliability of SSD RAID with unified SSD and HDD hybrid architecture.
Microprocess. Microsystems, 2024
2023
A Game-Theory Based Collision-Avoidance Solution for Two Automated Vehicles in Lane-Reduction Scenario.
Proceedings of the 5th International Conference on Robotics, 2023
Runtime Row/Column Activation Pruning for ReRAM-based Processing-in-Memory DNN Accelerators.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
2020
UniBuffer: Optimizing Journaling Overhead With Unified DRAM and NVM Hybrid Buffer Cache.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
2018
Comput. Networks, 2018
Proceedings of the Algorithms and Architectures for Parallel Processing, 2018
Proceedings of the Algorithms and Architectures for Parallel Processing, 2018
Proceedings of the 20th IEEE International Conference on High Performance Computing and Communications; 16th IEEE International Conference on Smart City; 4th IEEE International Conference on Data Science and Systems, 2018
2017
Proceedings of the 18th ACM SIGPLAN/SIGBED Conference on Languages, 2017
ESD-WSN: An Efficient SDN-Based Wireless Sensor Network Architecture for IoT Applications.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2017
Energy-Balanced and Depth-Controlled Routing Protocol for Underwater Wireless Sensor Networks.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2017
2016
Energy Efficient Real-Time Task Scheduling for Embedded Systems with Hybrid Main Memory.
J. Signal Process. Syst., 2016
J. Syst. Archit., 2016
Proceedings of the Network and Parallel Computing, 2016
Proceedings of the 19th IEEE International Conference on Intelligent Transportation Systems, 2016
Proceedings of the IEEE International Conference on Intelligent Transportation Engineering, 2016
Unified DRAM and NVM hybrid buffer cache architecture for reducing journaling overhead.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
A Novel OpenFlow-Based DDoS Flooding Attack Detection and Response Mechanism in Software-Defined Networking.
Int. J. Inf. Secur. Priv., 2015
Proceedings of the Algorithms and Architectures for Parallel Processing, 2015
AIMR: An Adaptive Page Management Policy for Hybrid Memory Architecture with NVM and DRAM.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015
2014
High Performance FPGA Implementation of Elliptic Curve Cryptography over Binary Fields.
Proceedings of the 13th IEEE International Conference on Trust, 2014
2012
Link Stability Evaluation and Stability Based Multicast Routing Protocol in Mobile Ad Hoc Networks.
Proceedings of the 11th IEEE International Conference on Trust, 2012