Zhixiang Chen
Affiliations:- Waseda University, Graduate School of Information Production and Systems, Kitakyushu, Japan
According to our database1,
Zhixiang Chen
authored at least 19 papers
between 2010 and 2015.
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Bibliography
2015
High-Throughput Power-Efficient VLSI Architecture of Fractional Motion Estimation for Ultra-HD HEVC Video Encoding.
IEEE Trans. Very Large Scale Integr. Syst., 2015
2014
High-Performance H.264/AVC Intra-Prediction Architecture for Ultra High Definition Video Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2014
2013
A 5.83pJ/bit/iteration High-Parallel Performance-Aware LDPC Decoder IP Core Design for WiMAX in 65nm CMOS.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
A 24.5-53.6pJ/pixel 4320p 60fps H.264/AVC intra-frame video encoder chip in 65nm CMOS.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
IPSJ Trans. Syst. LSI Des. Methodol., 2012
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
Proceedings of the Symposium on VLSI Circuits, 2012
An efficient majority-logic based message-passing algorithm for non-binary LDPC decoding.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
2011
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011
A high parallel macro block level layered LDPC decoding architecture based on dedicated matrix reordering.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
2010
A High Parallelism LDPC Decoder with an Early Stopping Criterion for WiMax and WiFi Application.
IPSJ Trans. Syst. LSI Des. Methodol., 2010
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
IEICE Trans. Electron., 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
High parallel variation Banyan network based permutation network for reconfigurable LDPC decoder.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010