Zhiwei Qin

According to our database, Zhiwei Qin authored at least 17 papers between 2010 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2016

An Adaptive Demand-Based Caching Mechanism for NAND Flash Memory Storage Systems.

Yi Wang, Zhiwei Qin, Renhai Chen, Zili Shao, Laurence T. Yang

ACM Trans. Design Autom. Electr. Syst., 2016

A Real-Time Flash Translation Layer for NAND Flash Memory Storage Systems.

Yi Wang, Zhiwei Qin, Renhai Chen, Zili Shao, Qixin Wang, Shuai Li, Laurence T. Yang

IEEE Trans. Multi Scale Comput. Syst., 2016

2015

On-Demand Block-Level Address Mapping in Large-Scale NAND Flash Storage Systems.

Renhai Chen, Zhiwei Qin, Yi Wang, Duo Liu, Zili Shao, Yong Guan

IEEE Trans. Computers, 2015

2013

Optimally Removing Intercore Communication Overhead for Streaming Applications on MPSoCs.

Yi Wang, Duo Liu, Zhiwei Qin, Zili Shao

IEEE Trans. Computers, 2013

2012

A Space Reuse Strategy for Flash Translation Layers in SLC NAND Flash Memory Storage Systems.

Duo Liu, Yi Wang, Zhiwei Qin, Zili Shao, Yong Guan

IEEE Trans. Very Large Scale Integr. Syst., 2012

Real-Time Flash Translation Layer for NAND Flash Memory Storage Systems.

Zhiwei Qin, Yi Wang, Duo Liu, Zili Shao

Proceedings of the 2012 IEEE 18th Real Time and Embedded Technology and Applications Symposium, 2012

A block-level flash memory management scheme for reducing write activities in PCM-based embedded systems.

Duo Liu, Tianzheng Wang, Yi Wang, Zhiwei Qin, Zili Shao

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

Overhead-aware energy optimization for real-time streaming applications on multiprocessor System-on-Chip.

Yi Wang, Hui Liu, Duo Liu, Zhiwei Qin, Zili Shao, Edwin Hsing-Mean Sha

ACM Trans. Design Autom. Electr. Syst., 2011

PCM-FTL: A Write-Activity-Aware NAND Flash Memory Management Scheme for PCM-Based Embedded Systems.

Duo Liu, Tianzheng Wang, Yi Wang, Zhiwei Qin, Zili Shao

Proceedings of the 32nd IEEE Real-Time Systems Symposium, 2011

A Two-Level Caching Mechanism for Demand-Based Page-Level Address Mapping in NAND Flash Memory Storage Systems.

Zhiwei Qin, Yi Wang, Duo Liu, Zili Shao

Proceedings of the 17th IEEE Real-Time and Embedded Technology and Applications Symposium, 2011

An endurance-enhanced Flash Translation Layer via reuse for NAND flash memory storage systems.

Yi Wang, Duo Liu, Zhiwei Qin, Zili Shao

Proceedings of the Design, Automation and Test in Europe, 2011

MNFTL: an efficient flash translation layer for MLC NAND flash memory storage systems.

Zhiwei Qin, Yi Wang, Duo Liu, Zili Shao, Yong Guan

Proceedings of the 48th Design Automation Conference, 2011

2010

Compiler-assisted leakage-aware loop scheduling for embedded VLIW DSP processors.

Meng Wang, Yi Wang, Duo Liu, Zhiwei Qin, Zili Shao

J. Syst. Softw., 2010

Memory-Aware Optimal Scheduling with Communication Overhead Minimization for Streaming Applications on Chip Multiprocessors.

Yi Wang, Duo Liu, Zhiwei Qin, Zili Shao

Proceedings of the 31st IEEE Real-Time Systems Symposium, 2010

Optimal Task Scheduling by Removing Inter-Core Communication Overhead for Streaming Applications on MPSoC.

Yi Wang, Duo Liu, Meng Wang, Zhiwei Qin, Zili Shao

Proceedings of the 16th IEEE Real-Time and Embedded Technology and Applications Symposium, 2010

RNFTL: a reuse-aware NAND flash translation layer for flash memory.

Yi Wang, Duo Liu, Meng Wang, Zhiwei Qin, Zili Shao, Yong Guan

Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, 2010

Demand-based block-level address mapping in large-scale NAND flash storage systems.

Zhiwei Qin, Yi Wang, Duo Liu, Zili Shao

Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010