Zhirui Zong

Orcid: 0000-0002-2681-0795

According to our database1, Zhirui Zong authored at least 10 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
DS-CIM: A 40nm Asynchronous Dual-Spike Driven, MRAM Compute-In-Memory Macro for Spiking Neural Network.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024

2023
A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit.
IEEE J. Solid State Circuits, 2023

2022
A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2021
A 21-to-41-GHz High-Gain Low Noise Amplifier With Triple-Coupled Technique for Multiband Wireless Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

2019
A Low-Noise Fractional- ${N}$ Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications.
IEEE J. Solid State Circuits, 2019

A 31-µW, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS.
IEEE J. Solid State Circuits, 2019

A Supply Pushing Reduction Technique for LC Oscillators Based on Ripple Replication and Cancellation.
IEEE J. Solid State Circuits, 2019

A 77/79-GHz Frequency Generator in 16-nm CMOS for FMCW Radar Applications Based on a 26-GHz Oscillator with Co-Generated Third Harmonic.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

2017
A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
A 60 GHz Frequency Generator Based on a 20 GHz Oscillator and an Implicit Multiplier.
IEEE J. Solid State Circuits, 2016


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