Zhiqiang You
Orcid: 0000-0001-9924-0685
According to our database1,
Zhiqiang You
authored at least 39 papers
between 2004 and 2024.
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Bibliography
2024
A Dynamic Weight Quantization-Based Fault-tolerant Training Method for Ternary Memristive Neural Networks.
Proceedings of the IEEE International Test Conference in Asia, 2024
A Scan Slice Reordering Algorithm Based on Minimizing Entropy to Enhance Test Data Compression Efficiency.
Proceedings of the IEEE International Test Conference in Asia, 2024
Proceedings of the IEEE International Test Conference in Asia, 2024
2023
Proceedings of the IEEE International Conference on Acoustics, 2023
2021
IEEE Trans. Emerg. Top. Comput., 2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
2020
A high-performance CNN method for offline handwritten Chinese character recognition and visualization.
Soft Comput., 2020
2019
Efficient data packet transmission algorithm for IPV6 mobile vehicle network based on fast switching model with time difference.
Future Gener. Comput. Syst., 2019
A Pseudo-Random Transform Decomposition Method for Improving the Coding Compression Ratio of Test Data.
Proceedings of the 21st IEEE International Conference on High Performance Computing and Communications; 17th IEEE International Conference on Smart City; 5th IEEE International Conference on Data Science and Systems, 2019
2018
IEICE Electron. Express, 2018
Eur. J. Control, 2018
Defect Analysis and Parallel March Test Algorithm for 3D Hybrid CMOS-Memristor Memory.
Proceedings of the 27th IEEE Asian Test Symposium, 2018
2016
A parallel-SSHI rectifier for ultra-low-voltage piezoelectric vibration energy harvesting.
IEICE Electron. Express, 2016
2015
Int. J. Circuit Theory Appl., 2015
Logic operation-based DFT method and 1R memristive crossbar March-like test algorithm.
IEICE Electron. Express, 2015
IEICE Electron. Express, 2015
Improve the compression ratios for code-based test vector compressions by decomposing.
Proceedings of the 20th IEEE European Test Symposium, 2015
2014
IEICE Electron. Express, 2014
CoRR, 2014
2013
A comprehensive metering scheme for intellectual property protection during both after-sale and evaluation periods of IC design.
IEICE Electron. Express, 2013
IEICE Electron. Express, 2013
2012
Achieving low capture and shift power in linear decompressor-based test compression environment.
Microelectron. J., 2012
Microelectron. J., 2012
Thermal Simulation of Traction System for High-Speed Train Based on Heat Accumulation.
J. Comput., 2012
IEICE Electron. Express, 2012
IEICE Electron. Express, 2012
2011
Microelectron. J., 2011
IEICE Electron. Express, 2011
2010
Proceedings of the IEEE 7th International Conference on e-Business Engineering, 2010
Proceedings of the Algorithms and Architectures for Parallel Processing, 2010
Capture in Turn Scan for Reduction of Test Data Volume, Test Application Time and Test Power.
Proceedings of the 19th IEEE Asian Test Symposium, 2010
2008
Test Response Data Volume and Wire Length Reductions for Extended Compatibilities Scan Tree Construction.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008
Proceedings of the 17th IEEE Asian Test Symposium, 2008
Proceedings of the 17th IEEE Asian Test Symposium, 2008
2006
IEICE Trans. Inf. Syst., 2006
2005
Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths.
IEICE Trans. Inf. Syst., 2005
2004
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004