Zhiqiang Que

Orcid: 0000-0002-9263-6529

According to our database1, Zhiqiang Que authored at least 50 papers between 2009 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Low Latency Variational Autoencoder on FPGAs.
IEEE J. Emerg. Sel. Topics Circuits Syst., June, 2024

LL-GNN: Low Latency Graph Neural Networks on FPGAs for High Energy Physics.
ACM Trans. Embed. Comput. Syst., March, 2024

Ultrafast jet classification at the HL-LHC.
Mach. Learn. Sci. Technol., 2024

Sets are all you need: Ultrafast jet classification on FPGAs for HL-LHC.
CoRR, 2024

Trustworthy Codesign by Verifiable Transformations.
Proceedings of the IEEE International Test Conference in Asia, 2024

2023
High-Performance Acceleration of 2-D and 3-D CNNs on FPGAs Using Static Block Floating Point.
IEEE Trans. Neural Networks Learn. Syst., August, 2023

Remarn: A Reconfigurable Multi-threaded Multi-core Accelerator for Recurrent Neural Networks.
ACM Trans. Reconfigurable Technol. Syst., March, 2023

When Monte-Carlo Dropout Meets Multi-Exit: Optimizing Bayesian Neural Networks on FPGA.
CoRR, 2023

Efficiently Removing Sparsity for High-Throughput Stream Processing.
Proceedings of the International Conference on Field Programmable Technology, 2023

MetaML: Automating Customizable Cross-Stage Design-Flow for Deep Learning Acceleration.
Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

When Monte-Carlo Dropout Meets Multi-Exit: Optimizing Bayesian Neural Networks on FPGA.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
Recurrent Neural Networks With Column-Wise Matrix-Vector Multiplication on FPGAs.
IEEE Trans. Very Large Scale Integr. Syst., 2022

Accelerating Bayesian Neural Networks via Algorithmic and Hardware Optimizations.
IEEE Trans. Parallel Distributed Syst., 2022

FPGA-Based Acceleration for Bayesian Convolutional Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

LL-GNN: Low Latency Graph Neural Networks on FPGAs for Particle Detectors.
CoRR, 2022

Customizable FPGA-based Accelerator for Binarized Graph Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Verifying Hardware Optimizations for Efficient Acceleration.
Proceedings of the HEART 2022: International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, Tsukuba, Japan, June 9, 2022

Accelerating Transformer Neural Networks on FPGAs for High Energy Physics Experiments.
Proceedings of the International Conference on Field-Programmable Technology, 2022

Optimizing Graph Neural Networks for Jet Tagging in Particle Physics on FPGAs.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

Algorithm and Hardware Co-design for Reconfigurable CNN Accelerator.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

Hardware-Aware Optimizations for Deep Learning Inference on Edge Devices.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2022

Reconfigurable Acceleration of Graph Neural Networks for Jet Identification in Particle Physics.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021
In-circuit tuning of deep learning designs.
J. Syst. Archit., 2021

Applications and Techniques for Fast Machine Learning in Science.
CoRR, 2021

High-Performance FPGA-based Accelerator for Bayesian Recurrent Neural Networks.
CoRR, 2021

Optimizing Bayesian Recurrent Neural Networks on an FPGA-based Accelerator.
Proceedings of the International Conference on Field-Programmable Technology, 2021

Flexible Instrumentation for Live On-Chip Debug of Machine Learning Training on FPGAs.
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

Accelerating Recurrent Neural Networks for Gravitational Wave Experiments.
Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021

2020
Mapping Large LSTMs to FPGAs with Weight Reuse.
J. Signal Process. Syst., 2020

Towards Overlay-based Rapid In-Circuit Tuning of Deep Learning Designs.
Proceedings of the International Conference on Field-Programmable Technology, 2020

A Reconfigurable Multithreaded Accelerator for Recurrent Neural Networks.
Proceedings of the International Conference on Field-Programmable Technology, 2020

Optimizing FPGA-Based CNN Accelerator Using Differentiable Neural Architecture Search.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

R2CNN: Recurrent Residual Convolutional Neural Network on FPGA.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

Optimizing Reconfigurable Recurrent Neural Networks.
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

High-Throughput Convolutional Neural Network on an FPGA by Customized JPEG Compression.
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

2019
An efficient convolutional neural network for small traffic sign detection.
J. Syst. Archit., 2019

Real-Time Anomaly Detection for Flight Testing Using AutoEncoder and LSTM.
Proceedings of the International Conference on Field-Programmable Technology, 2019

An Overlay for Rapid FPGA Debug of Machine Learning Applications.
Proceedings of the International Conference on Field-Programmable Technology, 2019

Towards In-Circuit Tuning of Deep Learning Designs.
Proceedings of the International Conference on Computer-Aided Design, 2019

Efficient Weight Reuse for Large LSTMs.
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

F-E3D: FPGA-based Acceleration of an Efficient 3D Convolutional Neural Network for Human Action Recognition.
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018
Reconfigurable Hardware Generation for Tensor Flow Models of CNN Algorithms on a Heterogeneous Acceleration Platform.
Proceedings of the Smart Computing and Communication - Third International Conference, 2018

Application of Transfer Learning in Continuous Time Series for Anomaly Detection in Commercial Aircraft Flight Data.
Proceedings of the 2018 IEEE International Conference on Smart Cloud, 2018

FPGA Acceleration of LSTM Based on Data for Test Flight.
Proceedings of the 2018 IEEE International Conference on Smart Cloud, 2018

Memory-Efficient Architecture for Accelerating Generative Networks on FPGA.
Proceedings of the International Conference on Field-Programmable Technology, 2018

A Real-Time Object Detection Accelerator with Compressed SSDLite on FPGA.
Proceedings of the International Conference on Field-Programmable Technology, 2018

Reconfigurable Acceleration of 3D-CNNs for Human Action Recognition with Block Floating-Point Representation.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2010
Revealing Feasibility of FMM on ASIC: Efficient Implementation of N-Body Problem on FPGA.
Proceedings of the 13th IEEE International Conference on Computational Science and Engineering, 2010

Implementing Medical CT Algorithms on Stand-alone FPGA Based Systems Using an Efficient Workflow with SysGen and Simulink.
Proceedings of the 10th IEEE International Conference on Computer and Information Technology, 2010

2009
Design and Implementation of a Cordless Power Supply System for Pervasive Medical Devices.
Proceedings of the International Conference on Embedded Software and Systems, 2009


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