Zhimin Zhang

Orcid: 0009-0000-8778-7149

Affiliations:

Chinese Academy of Sciences, State Key Laboratory of Computer Architecture, SKLCA, Institute of Computing Technology, Beijing, China

According to our database¹, Zhimin Zhang authored at least 22 papers between 2005 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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PhD thesis

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Bibliography

2024

Accelerating Mini-batch HGNN Training by Reducing CUDA Kernels.

[BibT_eX]

[DOI]

CoRR, 2024

JPlace: A Clock-Aware Length-Matching Placement for Rapid Single-Flux-Quantum Circuits.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

Design of a Compact Superconducting RSFQ Register File.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., November, 2023

Characterizing and Understanding Defense Methods for GNNs on GPUs.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2023

JRouter: A Multi-Terminal Hierarchical Length-Matching Router under Planar Manhattan Routing Model for RSFQ Circuits.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

2021

Equivalence Checking for Superconducting RSFQ Logic Circuits.

[BibT_eX]

[DOI]

Rongliang Fu

Junying Huang

Zhimin Zhang

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

2020

Characterizing and Understanding GCNs on GPU.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2020

HyGCN: A GCN Accelerator with Hybrid Architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

Design Automation Methodology from RTL to Gate-level Netlist and Schematic for RSFQ Logic Circuits.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

2019

Alleviating Irregularity in Graph Analytics Acceleration: a Hardware/Software Co-Design Approach.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Instruction Vulnerability Test and Code Optimization Against DVFS Attack.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2019

Balancing Memory Accesses for Energy-Efficient Graph Analytics Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

iATPG: Instruction-level Automatic Test Program Generation for Vulnerabilities under DVFS attack.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

2018

A Non-Stop Double Buffering Mechanism for Dataflow Architecture.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2018

High-Performance and Energy-Efficient Fault Tolerance Scheduling Algorithm Based on Improved TMR for Heterogeneous System.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Parallel & Distributed Processing with Applications, 2018

WEAVER: An Energy Efficient, General-Purpose Acceleration Architecture for String Operations in Big Data Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Parallel & Distributed Processing with Applications, 2018

2017

An Efficient Network-on-Chip Router for Dataflow Architecture.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2017

2016

An energy-efficient bandwidth allocation method for single-chip heterogeneous processor.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Green and Sustainable Computing Conference, 2016

A framework for energy-efficient optimization on multi-cores.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Green and Sustainable Computing Conference, 2016

Memory partition for SIMD in streaming dataflow architectures.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Green and Sustainable Computing Conference, 2016

POSTER: An Optimization of Dataflow Architectures for Scientific Applications.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016

2005

SoC Leakage Power Reduction Algorithm by Input Vector Control.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on System-on-Chip, 2005

Zhimin Zhang

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