Zhimin Chen

Affiliations:
  • Virginia Polytechnic Institute and State University, Blacksburg, VA, USA


According to our database1, Zhimin Chen authored at least 15 papers between 2008 and 2013.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2013
Using Virtual Secure Circuit to Protect Embedded Software from Side-Channel Attacks.
IEEE Trans. Computers, 2013

2011
SCA-Resistant and High-Performance Embedded Cryptography Using Instruction Set Extensions and Multi-Core Processors.
PhD thesis, 2011

A Parallel Implementation of Montgomery Multiplication on Multicore Systems: Algorithm, Analysis, and Prototype.
IEEE Trans. Computers, 2011

Data-oriented performance analysis of SHA-3 candidates on FPGA accelerated computers.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Virtual Secure Circuit: Porting Dual-Rail Pre-charge Technique into Software on Multicore.
IACR Cryptol. ePrint Arch., 2010

Combining multicore and reconfigurable instruction set extensions.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

pSHS: A scalable parallel software implementation of Montgomery multiplication for multicore systems.
Proceedings of the Design, Automation and Test in Europe, 2010

A comprehensive analysis of performance and side-channel-leakage of AES SBOX implementations in embedded software.
Proceedings of the 5th Workshop on Embedded Systems Security, 2010

Implementing virtual secure circuit using a custom-instruction approach.
Proceedings of the 2010 International Conference on Compilers, 2010

2009
Side-Channel Leakage in Masked Circuits Caused by Higher-Order Circuit Effects.
Proceedings of the Advances in Information Security and Assurance, 2009

Increasing the Sensitivity of On-Chip Digital Thermal Sensors with Pre-Filtering.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

Extended Abstract: Early Feedback on Side-Channel Risks with Accelerated Toggle-Counting.
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2009

2008
A Hardware Interface for Hashing Algorithms.
IACR Cryptol. ePrint Arch., 2008

Energy and Performance Evaluation of an FPGA-Based SoC Platform with AES and PRESENT Coprocessors.
Proceedings of the Embedded Computer Systems: Architectures, 2008

Slicing Up a Perfect Hardware Masking Scheme.
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2008


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