Zhiliang Qian
According to our database1,
Zhiliang Qian
authored at least 25 papers
between 2011 and 2021.
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Bibliography
2021
Simulation of Steady-State Temperature Rise of Electric Heating Field of Wireless Sensor Circuit Fault Current Trigger.
J. Sensors, 2021
2019
Reliability- and performance-driven mapping for regular 3D NoCs using a novel latency model and Simulated Allocation.
Integr., 2019
2017
M3A: Model, MetaModel and Anomaly Detection for Inter-arrivals of Web Searches and Postings.
Proceedings of the 2017 IEEE International Conference on Data Science and Advanced Analytics, 2017
BHNN: A memory-efficient accelerator for compressing deep neural networks with blocked hashing techniques.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
Performance Evaluation of NoC-Based Multicore Systems: From Traffic Analysis to NoC Latency Modeling.
ACM Trans. Design Autom. Electr. Syst., 2016
A Support Vector Regression (SVR)-Based Latency Model for Network-on-Chip (NoC) Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
BiLink: A high performance NoC router architecture using bi-directional link with double data rate.
Integr., 2016
A feature exploration methodology for learning based cuffless blood pressure measurement using photoplethysmography.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016
Live demonstration: A support vector machine based hardware platform for blood pressure prediction.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016
An FPGA-based morphological filter for baseline wandering correction in photoplethysmography.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016
LRADNN: High-throughput and energy-efficient Deep Neural Network accelerator using Low Rank Approximation.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
FSNoC: A Flit-Level Speedup Scheme for Network on-Chips Using Self-Reconfigurable Bidirectional Channels.
IEEE Trans. Very Large Scale Integr. Syst., 2015
2014
High Performance Network-on-Chips (NoCs) Design: Performance Modeling, Routing Algorithm and Architecture Optimization.
CoRR, 2014
An efficient Network-on-Chip (NoC) based multicore platform for hierarchical parallel genetic algorithms.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014
Disease Diagnosis-on-a-Chip: Large Scale Networks-on-Chip based Multicore Platform for Protein Folding Analysis.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
Performance evaluation of multicore systems: from traffic analysis to latency predictions (embedded tutorial).
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
SVR-NoC: a performance analysis tool for network-on-chips using learning-based support vector regression model.
Proceedings of the Design, Automation and Test in Europe, 2013
2012
A flit-level speedup scheme for network-on-chips using self-reconfigurable bi-directional channels.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
A traffic-aware adaptive routing algorithm on a highly reconfigurable network-on-chip architecture.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012
2011
A fault-tolerant NoC using combined link sharing and partial fault link utilization scheme.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
A fault-tolerant network-on-chip design using dynamic reconfiguration of partial-faulty routing resources.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011