Zhiguo Ge

According to our database, Zhiguo Ge authored at least 6 papers between 2003 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

Efficient Timestamp-Based Cache Coherence Protocol for Many-Core Architectures.

Yuan Yao, Guanhua Wang, Zhiguo Ge, Tulika Mitra, Wenzhi Chen, Naxin Zhang

Proceedings of the 2016 International Conference on Supercomputing, 2016

2015

SelectDirectory: a selective directory for cache coherence in many-core architectures.

Yuan Yao, Guanhua Wang, Zhiguo Ge, Tulika Mitra, Wenzhi Chen, Naxin Zhang

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2009

A DVS-based pipelined reconfigurable instruction memory.

Zhiguo Ge, Tulika Mitra, Weng-Fai Wong

Proceedings of the 46th Design Automation Conference, 2009

2007

DRIM: a low power dynamically reconfigurable instruction memory hierarchy for embedded systems.

Zhiguo Ge, Weng-Fai Wong, Hock-Beng Lim

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2005

A Reconfigurable Instruction Memory Hierarchy for Embedded Systems.

Zhiguo Ge, Hock-Beng Lim, Weng-Fai Wong

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2003

Compiling to FPGAs via an EPIC compiler's intermediate representation.

Zhiguo Ge, Jirong Liao, Weng-Fai Wong

Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003