Zhigang Mao

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

Enabling Resistive-RAM-based Activation Functions for Deep Neural Network Acceleration.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

2019

A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add Operations.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2019

Energy-Efficient Nonvolatile SRAM Design Based on Resistive Switching Multi-Level Cells.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2019

A Novel Memristor-Reusable Mapping Methodology of In-memory Logic Implementation for High Area-Efficiency.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

mRNA: Enabling Efficient Mapping Space Exploration for a Reconfiguration Neural Accelerator.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

Statistical Modeling and Design of a 16nm 9T SRAM Cell Considering Post-Synthesis Removal of Metallic Carbon-Nanotubes.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Electronics, Information, and Communication, 2019

Synergistic Effect of BTI and Process Variations on Impact and Monitoring of Combination Circuit.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

Carbon-Based Three-Dimensional SRAM Cell with Minimum Inter-Layer Area Skew Considering Process imperfections.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018

Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

MBSS: A General Paradigm for Static Schedule for Nested Loops with Dynamic Loop Boundary on CGRAs.

[BibT_eX]

[DOI]

Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

Optimizing the data placement and transformation for multi-bank CGRA computing system.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

In Situ Error Detection Techniques in Ultralow Voltage Pipelines: Analysis and Optimizations.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS Technology.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Variable strength keeper for high-speed and low-leakage carbon nanotube domino logic.

[BibT_eX]

[DOI]

Microelectron. J., 2017

Near- and Sub-V<sub>t</sub> Pipelines Based on Wide-Pulsed-Latch Design Techniques.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2017

Dynamic data split: A crosstalk suppression scheme in TSV-based 3D IC.

[BibT_eX]

[DOI]

Integr., 2017

A 12-bit 4928 × 3264 pixel CMOS image signal processor for digital still cameras.

[BibT_eX]

[DOI]

Integr., 2017

Low redundancy matrix-based codes for adjacent error correction with parity sharing.

[BibT_eX]

[DOI]

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

A static-placement, dynamic-issue framework for CGRA loop accelerator.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Reliability analysis of memories suffering MBUs for the effect of negative bias temperature instability.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Metallic-carbon-nanotube-removal tolerant SRAM cell with 9 transistors.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016

Extend orthogonal Latin square codes for 32-bit data protection in memory applications.

[BibT_eX]

[DOI]

Shanshan Liu

Microelectron. Reliab., 2016

Parallel SER analysis for combinational and sequential standard cell circuits.

[BibT_eX]

[DOI]

Jianfei Jiang

Microelectron. J., 2016

Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2016

High performance parallel turbo decoder with configurable interleaving network for LTE application.

[BibT_eX]

[DOI]

Integr., 2016

Area-efficient HEVC IDCT/IDST architecture for 8K × 4K video decoding.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2016

Enabling in-situ logic-in-memory capability using resistive-RAM crossbar memory.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

A 0.35V 1.3pJ/cycle 20MHz 8-bit 8-tap FIR core based on wide-pulsed-latch pipelines.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015

Soft Error Hardened Memory Design for Nanoscale Complementary Metal Oxide Semiconductor Technology.

[BibT_eX]

[DOI]

IEEE Trans. Reliab., 2015

Design and Implementation of Flexible Dual-Mode Soft-Output MIMO Detector With Channel Preprocessing.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Improved Iterative Receiver for Co-channel Interference Suppression in MIMO-OFDM Systems.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

Design optimization for capacitive-resistively driven on-chip global interconnect.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2015

Resource-saving compile flow for coarse-grained reconfigurable architectures.

[BibT_eX]

[DOI]

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Parasitic Parameters Impacts Investigation on Soft Error Rate by a Circuit Level Framework.

[BibT_eX]

[DOI]

Zhongyuan Zhao

Proceedings of the 21st IEEE Pacific Rim International Symposium on Dependable Computing, 2015

A contactless testing methodology for pre-bond interposer.

[BibT_eX]

[DOI]

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Fault Secure Encoder and Decoder Designs for Matrix Codes.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on Computer-Aided Design and Computer Graphics, 2015

A crosstalk avoidance scheme based on re-layout of signal TSV.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Fault detection and redundancy design for TSVs in 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014

Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Novel Low-Power and Highly Reliable Radiation Hardened Memory Cell for 65 nm CMOS Technology.

[BibT_eX]

[DOI]

Jing Guo

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Improved Max-Log-MAP BICM-IDD receiver for MIMO systems.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2014

Area and throughput efficient IDCT/IDST architecture for HEVC standard.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

Novel Mixed Codes for Multiple-Cell Upsets Mitigation in Static RAMs.

[BibT_eX]

[DOI]

IEEE Micro, 2013

A full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2013

A soft-output parallel stack algorithm for MIMO detection.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

Analysis of electromechanical interface model for liquid floated micro-gyroscope.

[BibT_eX]

[DOI]

Proceedings of the 8th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2013

A cost effective 2-D adaptive block size IDCT architecture for HEVC standard.

[BibT_eX]

[DOI]

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

An energy-efficient and scalable eDRAM-based register file architecture for GPGPU.

[BibT_eX]

[DOI]

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

A Block Cipher Circuit Design against Power Analysis.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Conference on Computational Intelligence and Security, 2013

A novel architecture scheme with adaptive pipeline coupling technique for DSP processor design.

[BibT_eX]

[DOI]

Zheng Tang

Proceedings of the IEEE 10th International Conference on ASIC, 2013

TSVs-aware floorplanning for 3D integrated circuit.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

Delay hidden techniques based on configuration contexts reuse and differential reconfiguration in coarse-grained reconfigurable processor.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012

SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2012

Novel O-GEHL Based Hyperblock Predictor for EDGE Architectures.

[BibT_eX]

[DOI]

Proceedings of the Seventh IEEE International Conference on Networking, 2012

Contention and energy aware mapping for real-time applications on Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2012

A pre-emphasis circuit design for high speed on-chip global interconnect.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Pareto Optimal Temporal Partition Methodology for Reconfigurable Architectures Based on Multi-objective Genetic Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

2011

Low Complexity Time Domain Interleaved Partitioning Partial Transmit Sequence Scheme for Peak-to-Average Power Ratio Reduction of Orthogonal Frequency Division Multiplexing Systems.

[BibT_eX]

[DOI]

Wirel. Pers. Commun., 2011

Companding schemes based on transforming signal statistics into trigonal distributions for PAPR reduction in OFDM systems.

[BibT_eX]

[DOI]

Int. J. Commun. Syst., 2011

On-chip structure and addressing scheme design for 2-D block data processing in a 64-core array system.

[BibT_eX]

[DOI]

Huimin Xing

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

A general statistical estimation for application mapping in Network-on-Chip.

[BibT_eX]

[DOI]

Naifeng Jing

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Robust design of sub-threshold flip-flop cells for wireless sensor network.

[BibT_eX]

[DOI]

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

A 230mV 8-bit sub-threshold microprocessor for wireless sensor network.

[BibT_eX]

[DOI]

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

A clock-less transceiver for global interconnect.

[BibT_eX]

[DOI]

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Parallel SFSD MIMO detection with SOFT-HARD combination enumeration.

[BibT_eX]

[DOI]

Jianpeng Yu

Jun Ma

Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

Generalized interleaving network based on configurable QPP architecture for parallel turbo decoder.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

A thermal-aware task mapping flow for coarse-grain dynamic reconfigurable processor.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Effective multi-standard macroblock prediction VLSI design for reconfigurable multimedia systems.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A novel low power 64-kb SRAM using bit-lines charge-recycling and non-uniform cell scheme.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Mitigating FPGA interconnect soft errors by in-place LUT inversion.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Fault modeling and characteristics of SRAM-based FPGAs (abstract only).

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

Efficient temporal task partition for coarse-grain reconfigurable systems based on Simulated Annealing Genetic Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

An efficient 90nm technology-node GHz transceiver of on-chip global interconnect.

[BibT_eX]

[DOI]

Zaixiao Zheng

Jianfei Jiang

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A reconfigurable linear array processor architecture for data parallel and computation intensive applications.

[BibT_eX]

[DOI]

Yucheng Liu

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A novel hardware prefetching scheme exploiting 2-D spatial locality in multimedia applications.

[BibT_eX]

[DOI]

Jin Huang

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010

Statistical estimation and evaluation for communication mapping in Network-on-Chip.

[BibT_eX]

[DOI]

Integr., 2010

Conjugate Interleaved Partitioning PTS Scheme for PAPR Reduction of OFDM Signals.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2010

Resource constrained mapping of data flow graphs onto coarse-grained reconfigurable array.

[BibT_eX]

[DOI]

Naifeng Jing

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

An efficient VLSI architecture for extended variable block sizes motion estimation.

[BibT_eX]

[DOI]

Weiwei Chen

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

2009

Statistical Estimation for Total Communication Load in Application-Specific Network-on-Chip.

[BibT_eX]

[DOI]

Naifeng Jing

Yongxin Zhu

Proceedings of the International Conference on Embedded Software and Systems, 2009

Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

2008

Versatile and Efficient Techniques for Speeding-Up Circuit Level Simulated Fault-Injection Campaigns.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE Pacific Rim International Symposium on Dependable Computing, 2008

A novel soft error sensitivity characterization technique based on simulated fault injection and constrained association analysis.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

A Hybrid Anti-Collision Algorithm for RFID with Enhanced Throughput and Reduced Memory Consumption.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE/IPIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), 2008

An Automated Fault Injection Technique Based on VHDL Syntax Analysis and Stratified Sampling.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

2007

A Scalable Frame-Level Pipelined Architecture for FSBM Motion Estimation.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

An Improved Frame-Level Pipelined Architecture for High Resolution Video Motion Estimation.

[BibT_eX]

[DOI]

Wei-Feng He

Zhi-Gang Mao

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A Link-Load Balanced Low Energy Mapping and Routing for NoC.

[BibT_eX]

[DOI]

Wenbiao Zhou

Yan Zhang

Proceedings of the Embedded Software and Systems, [Third] International Conference, 2007

2006

Efficient time-domain residual ISI cancellation for OFDM-based WLAN systems.

[BibT_eX]

[DOI]

Wei Zhong

IEEE Trans. Consumer Electron., 2006

A Restoration Algorithm for Images Contaminated by Impulse Noise.

[BibT_eX]

[DOI]

Peng Liu

Yan Zhang

J. Comput. Res. Dev., 2006

Pareto based Multi-objective Mapping IP Cores onto NoC Architectures.

[BibT_eX]

[DOI]

Wenbiao Zhou

Yan Zhang

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Design and VLSI Architecture of a Channel Equalizer Based on Adaptive Modulation for IEEE 802.11a WLAN.

[BibT_eX]

[DOI]

Wei Zhong

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

Efficient frame-level pipelined array architecture for full-search block-matching motion estimation.

[BibT_eX]

[DOI]

Yunlong Bi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

An adaptive motion estimation algorithm based on evolution strategies with correlated mutations.

[BibT_eX]

Hui Wang

Proceedings of the 2004 International Conference on Image Processing, 2004

An adaptive motion estimation algorithm based on evolution strategies.

[BibT_eX]

[DOI]

Hui Wang

Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

2000

Implementation of Java Card Virtual Machine.

[BibT_eX]

[DOI]

Liu Songyan

Yizheng Ye

J. Comput. Sci. Technol., 2000

1999

A New Algorithm for Retiming-Based Partial Scan.

[BibT_eX]

[DOI]

Zulan Huang

Yizheng Ye