Zhichun Zhu

ACM Trans. Design Autom. Electr. Syst., 2023

Redundant Array of Independent Memory Devices.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2023

2022

Dynamic Page Policy Using Perceptron Learning.

[BibT_eX]

[DOI]

Proceedings of the 2022 International Symposium on Memory Systems, 2022

2021

Memory-Side Prefetching Scheme Incorporating Dynamic Page Mode in 3D-Stacked DRAM.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2021

POMI: Polling-Based Memory Interface for Hybrid Memory System.

[BibT_eX]

[DOI]

Trung Le

Proceedings of the 39th IEEE International Conference on Computer Design, 2021

2020

DeepSwapper: A Deep Learning Based Page Swap Management Scheme for Hybrid Memory Systems.

[BibT_eX]

[DOI]

Proceedings of the PACT '20: International Conference on Parallel Architectures and Compilation Techniques, 2020

2019

Writeback-Aware LLC Management for PCM-Based Main Memory Systems.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2019

FAPS-3D: feedback-directed adaptive page management scheme for 3D-stacked DRAM.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Memory Systems, 2019

2018

CAMPS: Conflict-Aware Memory-Side Prefetching Scheme for Hybrid Memory Cube.

[BibT_eX]

[DOI]

Proceedings of the 47th International Conference on Parallel Processing, 2018

WALL: A writeback-aware LLC management for PCM-based main memory systems.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

NEMO: an energy-efficient hybrid main memory system for mobile devices.

[BibT_eX]

[DOI]

Bahareh Pourshirazi

Proceedings of the International Symposium on Memory Systems, 2017

2016

Refree: A Refresh-Free Hybrid DRAM/PCM Main Memory System.

[BibT_eX]

[DOI]

Bahareh Pourshirazi

Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium, 2016

2014

Mini-Rank: A Power-EfficientDDRx DRAM Memory Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

Access-Aware Memory Thermal Management.

[BibT_eX]

[DOI]

Suyu Zhang

Proceedings of the 9th IEEE International Conference on Networking, 2014

2013

Thermal Modeling and Management of DRAM Systems.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2013

Conservative row activation to improve memory power efficiency.

[BibT_eX]

[DOI]

Kun Fang

Proceedings of the International Conference on Supercomputing, 2013

2011

Memory Architecture for Integrating Emerging Memory Technologies.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010

Power and Performance Trade-Offs in Contemporary DRAM System Designs for Multicore Processors.

[BibT_eX]

[DOI]

Hongzhong Zheng

IEEE Trans. Computers, 2010

Heterogeneous Mini-rank: Adaptive, Power-Efficient Memory Architecture.

[BibT_eX]

[DOI]

Kun Fang

Hongzhong Zheng

Proceedings of the 39th International Conference on Parallel Processing, 2010

2009

Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices.

[BibT_eX]

[DOI]

Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

2008

Software thermal management of dram memory for multicore systems.

[BibT_eX]

[DOI]

Proceedings of the 2008 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, 2008

Mini-rank: Adaptive DRAM architecture for improving memory power efficiency.

[BibT_eX]

[DOI]

Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

Memory Access Scheduling Schemes for Systems with Multi-Core Processors.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Parallel Processing, 2008

2007

DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Symposium on Performance Analysis of Systems and Software, 2007

Thermal modeling and management of DRAM memory systems.

[BibT_eX]

[DOI]

Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

2005

Look-Ahead Architecture Adaptation to Reduce Processor Power Consumption.

[BibT_eX]

[DOI]

IEEE Micro, 2005

A Performance Comparison of DRAM Memory System Optimizations for SMT Processors.

[BibT_eX]

[DOI]

Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005

2004

Design and Optimization of Large Size and Low Overhead Off-Chip Caches.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2004

2002

Access-Mode Predictions for Low-Power Cache Design.

[BibT_eX]

[DOI]

IEEE Micro, 2002

Fine-Grain Priority Scheduling on Multi-Channel Memory Systems.

[BibT_eX]

[DOI]

Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002

2001

Cached DRAM for ILP Processor Memory Access Latency Reduction.

[BibT_eX]

[DOI]

IEEE Micro, 2001

Breaking Address Mapping Symmetry at Multi-levels of Memory Heirarchy to Reduce DRAM Row-buffer Conflicts.

[BibT_eX]

[DOI]

J. Instr. Level Parallelism, 2001

2000

Memory Hierarchy Considerations for Cost-Effective Cluster Computing.

[BibT_eX]

[DOI]

Xing Du

IEEE Trans. Computers, 2000

A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality.

[BibT_eX]

[DOI]