Zhichuan Guo

Orcid: 0000-0003-2489-9949

According to our database1, Zhichuan Guo authored at least 12 papers between 2012 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2025
RosebudVirt: A High-Performance and Partially Reconfigurable FPGA Virtualization Framework for Multitenant Networks.
IEEE Trans. Very Large Scale Integr. Syst., January, 2025

2024
An Implementation of Reconfigurable Match Table for FPGA-Based Programmable Switches.
IEEE Trans. Very Large Scale Integr. Syst., November, 2024

Fast Update Algorithm With Reorder Mechanism for SRAM-Based Longest Prefix Matching on FPGA.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

High-Throughput Exact Matching Implementation on FPGA with Shared Rule Tables Among Parallel Pipelines.
IEICE Trans. Commun., 2024

2023
High Performance Network Virtualization Architecture on FPGA SmartNIC.
IEICE Trans. Commun., June, 2023

2022
FGLB: A fine-grained hardware intra-server load balancer based on 100 G FPGA SmartNIC.
Int. J. Netw. Manag., 2022

2021
A Multifunctional Full-Packet Capture and Network Measurement System Supporting Nanosecond Timestamp and Real-Time Analysis.
IEEE Trans. Instrum. Meas., 2021

Accelerating the SM3 hash algorithm with CPU-FPGA Co-Designed architecture.
IET Comput. Digit. Tech., 2021

2020
Malware Traffic Classification Based on Recurrence Quantification Analysis.
Int. J. Netw. Secur., 2020

High-Performance Implementation of Dynamically Configurable Load Balancing Engine on FPGA.
IEEE Commun. Mag., 2020

2019
High Throughput Implementation of SMS4 on FPGA.
IEEE Access, 2019

2012
Efficient information hiding in H.264/AVC video coding.
Telecommun. Syst., 2012


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