Zhi-Wei Chen

Chen-Ning Yang

J. Inf. Sci. Eng., 2013

Routability-constrained multi-bit flip-flop construction for clock power reduction.

[BibT_eX]

[DOI]

Integr., 2013

Probabilistic Fatigue Assessment Based on Bayesian Learning for Wind-Excited Long-Span Bridges Installed with WASHMS.

[BibT_eX]

[DOI]

Xiao-Ming Wang

Int. J. Distributed Sens. Networks, 2013

Post-layout redundant wire insertion for fixing min-delay violations.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Timing-constrained replacement using spare cells for design changes.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2012

New optimal layer assignment for bus-oriented escape routing.

[BibT_eX]

[DOI]

Integr., 2012

Direction-constrained layer assignment for rectangle escape routing.

[BibT_eX]

[DOI]

Proceedings of the IEEE 25th International SOC Conference, 2012

Efficient assignment of inter-die signals for die-stacking SiP design.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Utilization of multi-bit flip-flops for clock power reduction.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Post-layout OPE-predicted redundant wire insertion for clock skew minimization.

[BibT_eX]

[DOI]

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Top-down-based symmetrical buffered clock routing.

[BibT_eX]

[DOI]

Ming-Chien Huang

Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Density-reduction-oriented layer assignment for rectangle escape routing.

[BibT_eX]

[DOI]

Jun-Min Chung

Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

2011

Simultaneous escape routing based on routability-driven net ordering.

[BibT_eX]

[DOI]

Tung-Yen Sung

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Obstacle-aware length-matching bus routing.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Symposium on Physical Design, 2011

RePEF - A system for Restoring Packed Executable File for malware analysis.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Machine Learning and Cybernetics, 2011

Pre-assignment RDL routing via extraction of maximal net sequence.

[BibT_eX]

[DOI]

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Genetic fuzzy markup language for diet application.

[BibT_eX]

[DOI]

Proceedings of the FUZZ-IEEE 2011, 2011

Obstacle-aware multiple-source rectilinear Steiner tree with electromigration and IR-drop avoidance.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Timing-constrained I/O buffer placement for flip-chip designs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Extending 3D Lucas-Kanade tracking with adaptive templates for head pose estimation.

[BibT_eX]

[DOI]

Zi-Tian Hsieh

Mach. Vis. Appl., 2010

Thermal via planning for temperature reduction in 3D ICs.

[BibT_eX]

[DOI]

Yu-Cheng Chang

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Routability-driven RDL routing with pin reassignment.

[BibT_eX]

[DOI]

Ke-Chyuan Chen

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Low-cost low-power bypassing-based multiplier design.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Width-constrained wire sizing for non-tree interconnections.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

The research of sampling frequency for A DC servo motor speed control system based on neural networks.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Conference on Natural Computation, 2010

Routability-driven flip-flop merging process for clock power reduction.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Computer Design, 2010

Ordered escape routing via routability-driven pin assignment.

[BibT_eX]

[DOI]

Chung-Wei Ke

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Resource-constrained timing-driven link insertion for critical delay reduction.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Property and application of fuzzy ontology for dietary assessment.

[BibT_eX]

[DOI]

Proceedings of the FUZZ-IEEE 2010, 2010

Two-sided single-detour untangling for bus routing.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

Obstacle-aware longest path using rectangular pattern detouring in routing grids.

[BibT_eX]

[DOI]

Ming-Ching Jhong

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Routability-driven partitioning-based IO assignment for flip-chip designs.

[BibT_eX]

[DOI]

Kai-Ping Lu

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009

Continuous K-Nearest Neighbor Query over Moving Objects in Road Networks.

[BibT_eX]

[DOI]

Yuan-Ko Huang

Chiang Lee

Proceedings of the Advances in Data and Web Management, Joint International Conferences, 2009

Low-power multiplier design with row and column bypassing.

[BibT_eX]

[DOI]

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Accurate Transformation-based Timing Analysis for RC Non-tree Circuits.

[BibT_eX]

[DOI]

Hsing-Lin Ko

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Redundant wire insertion for yield improvement.

[BibT_eX]

[DOI]

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

RDL pre-assignment routing for flip-chip designs.

[BibT_eX]

[DOI]

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

IO connection assignment and RDL routing for flip-chip designs.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Thermal-driven white space redistribution for block-level floorplans.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Simultaneous assignment of power pads and wires for reliability-driven hierarchical power quad-grids.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Flexible escape routing for flip-chip designs.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Timing-constrained yield-driven redundant via insertion.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Electromigration-aware rectilinear Steiner tree construction for analog circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Timing-driven multi-layer Steiner tree construction with obstacle avoidance.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007

Area-driven decoupling capacitance allocation based on space sensitivity analysis for signal integrity.

[BibT_eX]

[DOI]

Ming-Yuen Wu

Proceedings of the 2007 IEEE International SOC Conference, 2007

Area-Driven Decoupling Capacitance Allocation in Noise-Aware Floorplan for Signal Integrity.

[BibT_eX]

[DOI]

Ming-Yuen Wu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Timing-Driven Steiner Tree Construction with Wire Sizing, Buffer Insertion and Obstacle Avoidance.

[BibT_eX]

[DOI]

Shi-Qin Huang

Proceedings of the 14th IEEE International Conference on Electronics, 2007

Routability-Driven Track Routing for Coupling Capacitance Reduction.

[BibT_eX]

[DOI]

Kuen-Ming Lin

Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006

In this paper, an approach for deaf-people.

[BibT_eX]

[DOI]

Yu-Cheng Lin

Proceedings of the 18th International Conference on Pattern Recognition (ICPR 2006), 2006

Area-Driven White Space Distribution for Detailed Floorplan Design.

[BibT_eX]

[DOI]

Ming-Yuen Wu

Proceedings of the 13th IEEE International Conference on Electronics, 2006

Yield-Driven Redundant Via Insertion Based on Probabilistic Via-Connection Analysis.

[BibT_eX]

[DOI]

Bo-Yi Chiang

Proceedings of the 13th IEEE International Conference on Electronics, 2006

Design and implementation of a reconfigurable hardware for secure embedded systems.

[BibT_eX]

[DOI]

Kuen-Cheng Chiang

Jean Jyh-Jiun Shann

Proceedings of the 2006 ACM Symposium on Information, Computer and Communications Security, 2006

Optimal Network Analysis in Hierarchical Power Quad-Grids.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

Data classification with radial basis function networks based on a novel kernel density estimation algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Neural Networks, 2005

Region-Based Color Correction of Images.

[BibT_eX]

[DOI]

Chin-Hao Hsu