Zhezhi He

Orcid: 0000-0002-6357-236X

According to our database1, Zhezhi He authored at least 100 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
VSPIM: SRAM Processing-in-Memory DNN Acceleration via Vector-Scalar Operations.
IEEE Trans. Computers, October, 2024

A Progressive Subnetwork Searching Framework for Dynamic Inference.
IEEE Trans. Neural Networks Learn. Syst., March, 2024

Evolving Virtual World with Delta-Engine.
CoRR, 2024

SpikeZIP-TF: Conversion is All You Need for Transformer-based SNN.
Proceedings of the Forty-first International Conference on Machine Learning, 2024

CLLMs: Consistency Large Language Models.
Proceedings of the Forty-first International Conference on Machine Learning, 2024

Obtaining Optimal Spiking Neural Network in Sequence Learning via CRNN-SNN Conversion.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2024, 2024

Watt: A Write-Optimized RRAM-Based Accelerator for Attention.
Proceedings of the Euro-Par 2024: Parallel Processing, 2024

BKDSNN: Enhancing the Performance of Learning-Based Spiking Neural Networks Training with Blurred Knowledge Distillation.
Proceedings of the Computer Vision - ECCV 2024, 2024

PIMLC: Logic Compiler for Bit-Serial Based PIM.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

An Efficient Logic Operation Scheduler for Minimizing Memory Footprint of In-Memory SIMD Computation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
DTATrans: Leveraging Dynamic Token-Based Quantization With Accuracy Compensation Mechanism for Efficient Transformer Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023

SoBS-X: Squeeze-Out Bit Sparsity for ReRAM-Crossbar-Based Neural Network Accelerator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

Model Extraction Attacks on Split Federated Learning.
CoRR, 2023

HyAcc: A Hybrid CAM-MAC RRAM-based Accelerator for Recommendation Model.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023

GIM: Versatile GNN Acceleration with Reconfigurable Processing-in-Memory.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023

GPT-LS: Generative Pre-Trained Transformer with Offline Reinforcement Learning for Logic Synthesis.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023

XMG-GPPIC: Efficient and Robust General-Purpose Processing-in-Cache with XOR-Majority-Graph.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

PIMPR: PIM-based Personalized Recommendation with Heterogeneous Memory Hierarchy.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
Non-Structured DNN Weight Pruning - Is It Beneficial in Any Platform?
IEEE Trans. Neural Networks Learn. Syst., 2022

T-BFA: Targeted Bit-Flip Adversarial Weight Attack.
IEEE Trans. Pattern Anal. Mach. Intell., 2022

CP-ViT: Cascade Vision Transformer Pruning via Progressive Sparsity Prediction.
CoRR, 2022

Cross-layer Designs against Non-ideal Effects in ReRAM-based Processing-in-Memory System.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores.
Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022

DTQAtten: Leveraging Dynamic Token-based Quantization for Efficient Attention Architecture.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Self-Terminating Write of Multi-Level Cell ReRAM for Efficient Neuromorphic Computing.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

SATO: spiking neural network acceleration via temporal-oriented dataflow and architecture.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

EBSP: evolving bit sparsity patterns for hardware-friendly inference of quantized deep neural networks.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

PIM-DH: ReRAM-based processing-in-memory architecture for deep hashing acceleration.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

ResSFL: A Resistance Transfer Framework for Defending Model Inversion Attack in Split Federated Learning.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2022

HAWIS: Hardware-Aware Automated WIdth Search for Accurate, Energy-Efficient and Robust Binary Neural Network on ReRAM Dot-Product Engine.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
BISWSRBS: A Winograd-based CNN Accelerator with a Fine-grained Regular Sparsity Pattern and Mixed Precision Quantization.
ACM Trans. Reconfigurable Technol. Syst., 2021

Unary Coding and Variation-Aware Optimal Mapping Scheme for Reliable ReRAM-Based Neuromorphic Computing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

SME: ReRAM-based Sparse-Multiplication-Engine to Squeeze-Out Bit Sparsity of Neural Network.
CoRR, 2021

Elf: accelerate high-resolution mobile deep vision with content-aware parallel offloading.
Proceedings of the ACM MobiCom '21: The 27th Annual International Conference on Mobile Computing and Networking, 2021

MetaGater: Fast Learning of Conditional Channel Gated Networks via Federated Meta-Learning.
Proceedings of the IEEE 18th International Conference on Mobile Ad Hoc and Smart Systems, 2021

ReRAM-Sharing: Fine-Grained Weight Sharing for ReRAM-Based Deep Neural Network Accelerator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A Ternary Memristive Logic-in-Memory Design for Fast Data Scan.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

Improving Neural Network Efficiency via Post-training Quantization with Adaptive Floating-Point.
Proceedings of the 2021 IEEE/CVF International Conference on Computer Vision, 2021

SME: ReRAM-based Sparse-Multiplication-Engine to Squeeze-Out Bit Sparsity of Neural Network.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021

Bit-Transformer: Transforming Bit-level Sparsity into Higher Preformance in ReRAM-based Accelerator.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

NeurObfuscator: A Full-stack Obfuscation Tool to Mitigate Neural Architecture Stealing.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2021

Re2PIM: A Reconfigurable ReRAM-Based PIM Design for Variable-Sized Vector-Matrix Multiplication.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Energy-Efficient Hybrid-RAM with Hybrid Bit-Serial based VMM Support.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

RADAR: Run-time Adversarial Weight Attack Detection and Accuracy Recovery.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

PIMGCN: A ReRAM-Based PIM Design for Graph Convolutional Network Acceleration.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

KSM: Fast Multiple Task Adaption via Kernel-Wise Soft Mask Learning.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2021

AdaptiveGCN: Efficient GCN Through Adaptively Sparsifying Graphs.
Proceedings of the CIKM '21: The 30th ACM International Conference on Information and Knowledge Management, Virtual Event, Queensland, Australia, November 1, 2021

2020
Efficient and Secure Deep Learning Inference System: A Software and Hardware Co-design Perspective.
PhD thesis, 2020

MRIMA: An MRAM-Based In-Memory Accelerator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Sparse BD-Net: A Multiplication-less DNN with Sparse Binarized Depth-wise Separable Convolution.
ACM J. Emerg. Technol. Comput. Syst., 2020

A Progressive Sub-Network Searching Framework for Dynamic Inference.
CoRR, 2020

Network-based multi-task learning models for biomarker selection and cancer outcome prediction.
Bioinform., 2020

Processing-in-Memory Accelerator for Dynamic Neural Network with Run-Time Tuning of Accuracy, Power and Latency.
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

Robust Sparse Regularization: Defending Adversarial Attacks Via Regularized Sparse Network.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Non-uniform DNN Structured Subnets Sampling for Dynamic Inference.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Defending Bit-Flip Attack through DNN Weight Reconstruction.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

TBT: Targeted Neural Network Attack With Bit Trojan.
Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020

Defending and Harnessing the Bit-Flip Based Adversarial Weight Attack.
Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020

Harmonious Coexistence of Structured Weight Pruning and Ternarization for Deep Neural Networks.
Proceedings of the Thirty-Fourth AAAI Conference on Artificial Intelligence, 2020

2019
Non-structured DNN Weight Pruning Considered Harmful.
CoRR, 2019

Robust Sparse Regularization: Simultaneously Optimizing Neural Network Robustness and Compactness.
CoRR, 2019

Bit-Flip Attack: Crushing Neural Network withProgressive Bit Search.
CoRR, 2019

Optimize Deep Convolutional Neural Network with Ternarized Weights and High Accuracy.
Proceedings of the IEEE Winter Conference on Applications of Computer Vision, 2019

Accelerating Deep Neural Networks in Processing-in-Memory Platforms: Analog or Digital Approach?
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Bit-Flip Attack: Crushing Neural Network With Progressive Bit Search.
Proceedings of the 2019 IEEE/CVF International Conference on Computer Vision, 2019

Binarized Depthwise Separable Neural Network for Object Tracking in FPGA.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Artificial Neuron using Ag/2D-MoS2/Au Threshold Switching Memristor.
Proceedings of the Device Research Conference, 2019

Noise Injection Adaption: End-to-End ReRAM Crossbar Non-ideal Effect Adaption for Neural Network Mapping.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Parametric Noise Injection: Trainable Randomness to Improve Deep Neural Network Robustness Against Adversarial Attack.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2019

Simultaneously Optimizing Weight and Quantizer of Ternary Neural Network Using Truncated Gaussian Approximation.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2019

ParaPIM: a parallel processing-in-memory accelerator for binary-weight deep neural networks.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Exploring a SOT-MRAM Based In-Memory Computing for Data Processing.
IEEE Trans. Multi Scale Comput. Syst., 2018

Design and Evaluation of a Spintronic In-Memory Processing Platform for Nonvolatile Data Encryption.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Blind Pre-Processing: A Robust Defense Method Against Adversarial Examples.
CoRR, 2018

BD-NET: A Multiplication-Less DNN with Binarized Depthwise Separable Convolution.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Accelerating Low Bit-Width Deep Convolution Neural Network in MRAM.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

A Fully Onchip Binarized Convolutional Neural Network FPGA Impelmentation with Accurate Inference.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

PIM-TGAN: A Processing-in-Memory Accelerator for Ternary Generative Adversarial Networks.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

DIMA: a depthwise CNN in-memory accelerator.
Proceedings of the International Conference on Computer-Aided Design, 2018

Leveraging Spintronic Devices for Efficient Approximate Logic and Stochastic Neural Networks.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

CMP-PIM: an energy-efficient comparator-based processing-in-memory neural network accelerator.
Proceedings of the 55th Annual Design Automation Conference, 2018

PIMA-logic: a novel processing-in-memory architecture for highly flexible and energy-efficient logic computation.
Proceedings of the 55th Annual Design Automation Conference, 2018

HielM: Highly flexible in-memory computing using STT MRAM.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

IMCE: Energy-efficient bit-wise in-memory convolution engine for deep neural network.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Energy Efficient Reconfigurable Threshold Logic Circuit with Spintronic Devices.
IEEE Trans. Emerg. Top. Comput., 2017

Developing All-Skyrmion Spiking Neural Network.
CoRR, 2017

Current Induced Dynamics of Multiple Skyrmions with Domain Wall Pair and Skyrmion-based Majority Gate Design.
CoRR, 2017

High performance and energy-efficient in-memory computing architecture based on SOT-MRAM.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

Leveraging spintronic devices for ultra-low power in-memory computing: Logic and neural network.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Hybrid Polymorphic Logic Gate with 5-Terminal Magnetic Domain Wall Motion Device.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

In-Memory Computing with Spintronic Devices.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

RIMPA: A New Reconfigurable Dual-Mode In-Memory Processing Architecture with Spin Hall Effect-Driven Domain Wall Motion Device.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Composite spintronic accuracy-configurable adder for low power Digital Signal Processing.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Low power in-memory computing based on dual-mode SOT-MRAM.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Hybrid polymorphic logic gate using 6 terminal magnetic domain wall motion device.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Exploring STT-MRAM Based In-Memory Computing Paradigm with Application of Image Edge Extraction.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Leveraging Dual-Mode Magnetic Crossbar for Ultra-low Energy In-memory Data Encryption.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Energy Efficient In-Memory Computing Platform Based on 4-Terminal Spin Hall Effect-Driven Domain Wall Motion Devices.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

A tunable magnetic skyrmion neuron cluster for energy efficient artificial neural network.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
A Low Power Current-Mode Flash ADC with Spin Hall Effect based Multi-Threshold Comparator.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016


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