Zhenyu Qi

Affiliations:
  • University of California Riverside, Riverside, CA, USA


According to our database1, Zhenyu Qi authored at least 12 papers between 2004 and 2006.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2006
Wideband passive multiport model order reduction and realization of RLCM circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

2005
Hierarchical approach to exact symbolic analysis of large analog circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Passive Hierarchical Model Order Reduction and Realization of RLCM Circuits.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Efficient Thermal Simulation for Run-Time Temperature Tracking and Management.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

An efficient method for terminal reduction of interconnect circuits considering delay variations.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Fast thermal simulation for architecture level dynamic thermal management.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Partitioning-based approach to fast on-chip decap budgeting and minimization.
Proceedings of the 42nd Design Automation Conference, 2005

A wideband hierarchical circuit reduction for massively coupled interconnects.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Hierarchical Modeling and Simulation of Large Analog Circuits.
Proceedings of the 2004 Design, 2004


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