Zheng Yu

Affiliations:
  • Fudan University, State Key Lab of ASIC and System, Shanghai, China


According to our database1, Zheng Yu authored at least 6 papers between 2013 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2014
Low-Power Multicore Processor Design With Reconfigurable Same-Instruction Multiple Process.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

A 16-Core Processor With Shared-Memory and Message-Passing Communications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

2013
Efficient distributed memory management in a multi-core H.264 decoder on FPGA.
Proceedings of the 2013 International Symposium on System on Chip, 2013

A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A low power register file with asynchronously controlled read-isolation and software-directed write-discarding.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

H.264 video parallel decoder on a 24-core processor.
Proceedings of the IEEE 10th International Conference on ASIC, 2013


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