Zheng Wang

Orcid: 0000-0003-2855-9570

Affiliations:
  • Chinese Academy of Sciences, Shenzhen Institutes of Advanced Technology, Center for Automotive Electronics, China
  • RWTH Aachen, Germany (PhD 2015)


According to our database1, Zheng Wang authored at least 27 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
AnchorCapsule: A Datastream-Serving Post-Processor for Object Detection in Embedded Vision SoC.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2024

Structure-Enhanced Protein Instruction Tuning: Towards General-Purpose Protein Understanding.
CoRR, 2024

Harmonizing Unets: Attention Fusion module in cascaded-Unets for low-quality OCT image fluid segmentation.
Comput. Biol. Medicine, 2024

Low-latency Buffering for Mixed-precision Neural Network Accelerator with MulTAP and FQPipe.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

PerFT-N: Low-overhead Permanent Fault-Tolerance Mechanism for Neural Processing Units.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

2023
Multi-Attention Feature Fusion Network for Accurate Estimation of Finger Kinematics From Surface Electromyographic Signals.
IEEE Trans. Hum. Mach. Syst., 2023

COMPACT: Co-processor for Multi-mode Precision-adjustable Non-linear Activation Functions.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
An Energy-Efficient Method for Recurrent Neural Network Inference in Edge Cloud Computing.
Symmetry, 2022

LIPFD-NPU: Low-overhead Instruction-driven Permanent Fault Detection for Neural Processing Unit.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

Context-Enhanced Stereo Transformer.
Proceedings of the Computer Vision - ECCV 2022, 2022

Colorization for in situ Marine Plankton Images.
Proceedings of the Computer Vision - ECCV 2022, 2022

2021
sEMG-Based Gesture Recognition Using GRU With Strong Robustness Against Forearm Posture.
Proceedings of the IEEE International Conference on Real-time Computing and Robotics, 2021

CNN-DMA: A Predictable and Scalable Direct Memory Access Engine for Convolutional Neural Network with Sliding-window Filtering.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

OR-ML: Enhancing Reliability for Machine Learning Accelerator with Opportunistic Redundancy.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Highly-accurate gesture recognition based on ResNet with low-budget data gloves.
Proceedings of the AISS 2021: 3rd International Conference on Advanced Information Science and System, Sanya, China, November 26, 2021

Improving system latency of AI accelerator with on-chip pipelined activation preprocessing and multi-mode batch inference.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2020
Accelerating Atrous Convolution with Fetch-and-Jump Architecture for Activation Positioning.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020

2019
Detecting Fault Injection Attacks Based on Compressed Sensing and Integer Linear Programming.
IEEE Trans. Dependable Secur. Comput., 2019

A 2.86-TOPS/W Current Mirror Cross-Bar-Based Machine-Learning and Physical Unclonable Function Engine For Internet-of-Things Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Accelerating Compact Convolutional Neural Networks with Multi-threaded Data Streaming.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

A Current Mirror Cross Bar Based 2.86-TOPS/W Machine Learner and PUF with <2.5% BER in 65nm CMOS for IoT Application.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Current Mirror Array: A Novel Circuit Topology for Combining Physical Unclonable Function and Machine Learning.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

2017
Current mirror array: A novel lightweight strong PUF topology with enhanced reliability.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
Low-Cost Hardware Infrastructure for Runtime Thread Level Energy Accounting.
Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016

2015
High-level estimation and exploration of reliability for multi-processor system-on-chip.
PhD thesis, 2015

Direct FPGA-based power profiling for a RISC processor.
Proceedings of the 2015 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings, 2015

2013
Power modeling and estimation during ADL-driven embedded processor design.
Proceedings of the 4th Annual International Conference on Energy Aware Computing Systems and Applications, 2013


  Loading...