Zheng Pei Wu

According to our database, Zheng Pei Wu authored at least 5 papers between 2013 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2016

Schedulability Analysis for Memory Bandwidth Regulated Multicore Real-Time Systems.

Gang Yao, Heechul Yun, Zheng Pei Wu, Rodolfo Pellizzoni, Marco Caccamo, Lui Sha

IEEE Trans. Computers, 2016

A composable worst case latency analysis for multi-rank DRAM devices under open row policy.

Zheng Pei Wu, Rodolfo Pellizzoni, Danlu Guo

Real Time Syst., 2016

2014

PALLOC: DRAM bank-aware memory allocator for performance isolation on multicore platforms.

Heechul Yun, Renato Mancuso, Zheng Pei Wu, Rodolfo Pellizzoni

Proceedings of the 20th IEEE Real-Time and Embedded Technology and Applications Symposium, 2014

A Rank-Switching, Open-Row DRAM Controller for Time-Predictable Systems.

Yogen Krishnapillai, Zheng Pei Wu, Rodolfo Pellizzoni

Proceedings of the 26th Euromicro Conference on Real-Time Systems, 2014

2013

Worst Case Analysis of DRAM Latency in Multi-requestor Systems.

Zheng Pei Wu, Yogen Krish, Rodolfo Pellizzoni

Proceedings of the IEEE 34th Real-Time Systems Symposium, 2013