Zhen Gao

Orcid: 0000-0001-9887-1418

Affiliations:
  • Tianjin University, School of Electrical and Information Engineering, China


According to our database1, Zhen Gao authored at least 39 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Modular-Based Compression Scheme for Address Data in the Blockchain System for IoV Applications.
IEEE Trans. Veh. Technol., October, 2024

Speed and Conversational Large Language Models: Not All Is About Tokens per Second.
Computer, August, 2024

Cognitive Data Fusing for Internet of Things Based on Ensemble Learning and Federated Learning.
IEEE Internet Things J., July, 2024

Verkle-Accumulator-Based Stateless Transaction Validation (VA-STV) Scheme for the Blockchain-Based IoT Network.
IEEE Internet Things J., January, 2024

Game-Based Low Complexity and Near Optimal Task Offloading for Mobile Blockchain Systems.
IEEE Trans. Cloud Comput., 2024

Harnessing Tullock Contests and Signaling Games: A Novel Weight Assignment Strategy for Ethereum 2.0.
IEEE Open J. Commun. Soc., 2024

CSI-GPT: Integrating Generative Pre-Trained Transformer with Federated-Tuning to Acquire Downlink Massive MIMO Channels.
CoRR, 2024

Reducing the Energy Dissipation of Large Language Models (LLMs) with Approximate Memories.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
World State Attack to Blockchain Based IoV and Efficient Protection With Hybrid RSUs Architecture.
IEEE Trans. Intell. Transp. Syst., September, 2023

Efficient Protection of FPGA Implemented LDPC Decoders Against Single Event Upsets (SEUs) on Configuration Memories.
IEEE Trans. Circuits Syst. I Regul. Pap., September, 2023

A Methodology for the Design of Fault Tolerant Parallel Digital Channelizers on SRAM-FPGAs.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023

Reliability Evaluation and Fault Tolerance Design for FPGA Implemented Reed Solomon (RS) Erasure Decoders.
IEEE Trans. Very Large Scale Integr. Syst., 2023

Resource Management and Pricing for Cloud Computing Based Mobile Blockchain With Pooling.
IEEE Trans. Cloud Comput., 2023

Promoting the Sustainability of Blockchain in Web 3.0 and the Metaverse Through Diversified Incentive Mechanism Design.
IEEE Open J. Comput. Soc., 2023

Concurrent Classifier Error Detection (CCED) in Large Scale Machine Learning Systems.
CoRR, 2023

2022
Soft Error Tolerant Convolutional Neural Networks on FPGAs With Ensemble Learning.
IEEE Trans. Very Large Scale Integr. Syst., 2022

RNS-Based Adaptive Compression Scheme for the Block Data in the Blockchain for IIoT.
IEEE Trans. Ind. Informatics, 2022

Fault Tolerant Polyphase Filters-Based Decimators for SRAM-Based FPGA Implementations.
IEEE Trans. Emerg. Top. Comput., 2022

Fault-Tolerant Deep Learning: A Hierarchical Perspective.
CoRR, 2022

Special Session: Fault-Tolerant Deep Learning: A Hierarchical Perspective.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022

Evaluation of Blockchain-enabled Mobile Core Network Control Plane for Satellite-terrestrial Integrated Networks.
Proceedings of the IEEE International Conference on Communications, 2022

A Blockchain-based Containerized Mobile Communication Testbed on Open Cloud Platform.
Proceedings of the 2022 IEEE International Conference on Communications Workshops, 2022

Evaluation of the Effects of SEUs on Configuration Memories in FPGA Implemented QC-LDPC Decoders.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022

2021
Design of FPGA-Implemented Reed-Solomon Erasure Code (RS-EC) Decoders With Fault Detection and Location on User Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2021

FTT-NAS: Discovering Fault-tolerant Convolutional Neural Architecture.
ACM Trans. Design Autom. Electr. Syst., 2021

Reliability Evaluation of the Count Min Sketch (CMS) against Single Event Transients (SETs).
Proceedings of the 39th IEEE VLSI Test Symposium, 2021

Reliability Evaluation of Digital Channelizers Implemented on SRAM - FPGAs.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

Analysis and Evaluation of the Effects of Single Event Upsets (SEU s) on Memories in Polar Decoders.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

Ensemble of Pruned Networks for Reliable Classifiers.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2020
Design of SEU-Tolerant Turbo Decoders Implemented on SRAM-FPGAs.
IEEE Trans. Very Large Scale Integr. Syst., 2020

FTT-NAS: Discovering Fault-Tolerant Neural Architecture.
CoRR, 2020

Reliable Classification with Ensemble Convolutional Neural Networks.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

Reliability Evaluation of Pruned Neural Networks against Errors on Parameters.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

Soft Error Mitigation for Deep Convolution Neural Network on FPGA Accelerators.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020

2018
An Efficient Fault-Tolerance Design for Integer Parallel Matrix-Vector Multiplications.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Efficient Fault-Tolerant Design for Parallel Matched Filters.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A Scheme to Design Concurrent Error Detection Techniques for the Fast Fourier Transform Implemented in SRAM-Based FPGAs.
IEEE Trans. Computers, 2018

2015
Secrecy Analysis on Network Coding in Bidirectional Multibeam Satellite Communications.
CoRR, 2015

2014
A fault tolerant implementation of the Goertzel algorithm.
Microelectron. Reliab., 2014


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