Zhen Fang

Affiliations:
  • Nvidia Corporation, Santa Clara, USA
  • University of Utah, USA (PhD 2006)


According to our database1, Zhen Fang authored at least 26 papers between 2000 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2013
Reducing cache and TLB power by exploiting memory region and privilege level semantics.
J. Syst. Archit., 2013

2012
Active memory controller.
J. Supercomput., 2012

Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

Reducing L1 caches power by exploiting software semantics.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Exploiting Semantics of Virtual Memory to Improve the Efficiency of the On-Chip Memory System.
Proceedings of the Euro-Par 2012 Parallel Processing - 18th International Conference, 2012

2011
CogniServe: Heterogeneous Server Architecture for Large-Scale Recognition.
IEEE Micro, 2011

ISIS: An accelerator for Sphinx speech recognition.
Proceedings of the IEEE 9th Symposium on Application Specific Processors, 2011

Cost-effectively offering private buffers in SoCs and CMPs.
Proceedings of the 25th International Conference on Supercomputing, 2011, Tucson, AZ, USA, May 31, 2011

ACCESS: Smart scheduling for asymmetric cache CMPs.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

Buffer-integrated-Cache: a cost-effective SRAM architecture for handheld and embedded platforms.
Proceedings of the 48th Design Automation Conference, 2011

Template-based memory access engine for accelerators in SoCs.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Boomerang: Reducing Power Consumption of Response Packets in NoCs with Minimal Performance Impact.
IEEE Comput. Archit. Lett., 2010

Performance characterization and acceleration of Optical Character Recognition on handheld platforms.
Proceedings of the 2010 IEEE International Symposium on Workload Characterization, 2010

2009
Performance characterization and optimization of mobile augmented reality on handheld platforms.
Proceedings of the 2009 IEEE International Symposium on Workload Characterization, 2009

Accelerating mobile augmented reality on a handheld platform.
Proceedings of the 27th International Conference on Computer Design, 2009

Using checksum to reduce power consumption of display systems for low-motion content.
Proceedings of the 27th International Conference on Computer Design, 2009

2007
Active memory operations.
Proceedings of the 21th Annual International Conference on Supercomputing, 2007

2006
Active Memory Operations.
PhD thesis, 2006

2005
Fast synchronization on shared-memory multiprocessors: An architectural approach.
J. Parallel Distributed Comput., 2005

2004
Scalable barrier synchronisation for large-scale shared-memory multiprocessors.
Int. J. High Perform. Comput. Netw., 2004

Highly Efficient Synchronization Based on Active Memory Operations.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

2003
An MPEG-4 performance study for non-SIMD, general purpose architectures.
Proceedings of the 2003 IEEE International Symposium on Performance Analysis of Systems and Software, 2003

A low-power accelerator for the SPHINX 3 speech recognition system.
Proceedings of the International Conference on Compilers, 2003

2001
The Impulse Memory Controller.
IEEE Trans. Computers, 2001

Reevaluating Online Superpage Promotion with Hardware Support.
Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001

2000
Online superpage promotion revisited (poster).
Proceedings of the 2000 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, 2000


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