Zhechong Lan

According to our database1, Zhechong Lan authored at least 5 papers between 2019 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2022
Theoretical total harmonic distortion evaluation based on digital to analogue converter mismatch to improve the linearity of successive approximation register analogue to digital converter.
IET Circuits Devices Syst., 2022

2021
A 98.1-dB SNDR 188-dB FoMS Noise-Shaping SAR ADC Using Series Connection Capacitors.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

A 12-Bit 100MS/s SAR ADC with Digital Error Correction and High-Speed LMS-Based Background Calibration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
A Two-step SAR ADC with Synchronous DEM Calibration Achieving Up to 15% Power Reduction.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020

2019
A Multi-Channel 1.52 µVrms Front End with Orthogonal Frequency Chopping for Neural Recording Applications.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019


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