Zhe Wang

According to our database, Zhe Wang authored at least 16 papers between 2011 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

Going Further With Winograd Convolutions: Tap-Wise Quantization for Efficient Inference on 4x4 Tile.

Renzo Andri, Beatrice Bussolino, Antonio Cipolletta, Lukas Cavigelli, Zhe Wang

CoRR, 2022

Identifying and Exploiting Sparse Branch Correlations for Optimizing Branch Prediction.

Anastasios Zouzias, Kleovoulos Kalaitzidis, Konstantin Berestizshevsky, Renzo Andri, Leeor Peled, Zhe Wang

CoRR, 2022

AgileWatts: An Energy-Efficient CPU Core Idle-State Architecture for Latency-Sensitive Server Applications.

Jawad Haj-Yahya, Haris Volos, Davide B. Bartolini, Georgia Antoniou, Jeremie S. Kim, Zhe Wang, Kleovoulos Kalaitzidis, Tom Rollet, Zhirui Chen, Ye Geng, Onur Mutlu, Yiannakis Sazeides

Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

Going Further With Winograd Convolutions: Tap-Wise Quantization for Efficient Inference on 4x4 Tiles.

Renzo Andri, Beatrice Bussolino, Antonio Cipolletta, Lukas Cavigelli, Zhe Wang

Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

2018

Flexible associativity for DRAM caches.

Elvira Teran, Zeshan Chishti, Zhe Wang, Chris Wilkerson, Daniel A. Jiménez

Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018

2017

Detecting and mitigating data-dependent DRAM failures by exploiting current memory content.

Samira Manabi Khan, Chris Wilkerson, Zhe Wang, Alaa R. Alameldeen, Donghyuk Lee, Onur Mutlu

Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

2016

Building a Low Latency, Highly Associative DRAM Cache with the Buffered Way Predictor.

Zhe Wang, Daniel A. Jiménez, Tao Zhang, Gabriel H. Loh, Yuan Xie

Proceedings of the 28th International Symposium on Computer Architecture and High Performance Computing, 2016

Perceptron learning for reuse prediction.

Elvira Teran, Zhe Wang, Daniel A. Jiménez

Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Minimal disturbance placement and promotion.

Elvira Teran, Yingying Tian, Zhe Wang, Daniel A. Jiménez

Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

2014

Adaptive placement and migration policy for an STT-RAM-based hybrid cache.

Zhe Wang, Daniel A. Jiménez, Cong Xu, Guangyu Sun, Yuan Xie

Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2013

WADE: Writeback-aware dynamic cache management for NVM-based main memory system.

Zhe Wang, Shuchang Shan, Ting Cao, Junli Gu, Yi Xu, Shuai Mu, Yuan Xie, Daniel A. Jiménez

ACM Trans. Archit. Code Optim., 2013

2012

Rank idle time prediction driven last-level cache writeback.

Zhe Wang, Samira Manabi Khan, Daniel A. Jiménez

Proceedings of the 2012 ACM SIGPLAN workshop on Memory Systems Performance and Correctness: held in conjunction with PLDI '12, 2012

Improving writeback efficiency with decoupled last-write prediction.

Zhe Wang, Samira Manabi Khan, Daniel A. Jiménez

Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

Decoupled dynamic cache segmentation.

Samira Manabi Khan, Zhe Wang, Daniel A. Jiménez

Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

2011

Exploiting Rank Idle Time for Scheduling Last-Level Cache Writeback.

Zhe Wang, Daniel A. Jiménez

Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

Program Interferometry.

Zhe Wang, Daniel A. Jiménez

Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011