Zhaori Bi
Orcid: 0000-0002-7315-3150
According to our database1,
Zhaori Bi
authored at least 23 papers
between 2013 and 2025.
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Bibliography
2025
IEEE Trans. Very Large Scale Integr. Syst., January, 2025
2024
Multiagent Based Reinforcement Learning (MA-RL): An Automated Designer for Complex Analog Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024
ROI-HIT: Region of Interest-Driven High-Dimensional Microarchitecture Design Space Exploration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2024
D<sup>3</sup>PBO: Dynamic Domain Decomposition-based Parallel Bayesian Optimization for Large-scale Analog Circuit Sizing.
ACM Trans. Design Autom. Electr. Syst., May, 2024
BBGP-sDFO: Batch Bayesian and Gaussian Process Enhanced Subspace Derivative Free Optimization for High-Dimensional Analog Circuit Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2024
pNeurFill: Enhanced Neural Network Model-Based Dummy Filling Synthesis With Perimeter Adjustment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2024
CoRR, 2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
tSS-BO: Scalable Bayesian Optimization for Analog Circuit Sizing via Truncated Subspace Sampling.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
EVDMARL: Efficient Value Decomposition-based Multi-Agent Reinforcement Learning with Domain-Randomization for Complex Analog Circuit Design Migration.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
HiMOSS: A Novel High-dimensional Multi-objective Optimization Method via Adaptive Gradient-Based Subspace Sampling for Analog Circuit Sizing.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
Asynchronous Batch Constrained Multi-Objective Bayesian Optimization for Analog Circuit Sizing.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
A Study on Exploring and Exploiting the High-dimensional Design Space for Analog Circuit Design Automation : (Invited Paper).
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
2023
A Batched Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-Fidelity Modeling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023
cVTS: A Constrained Voronoi Tree Search Method for High Dimensional Analog Circuit Synthesis.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2022
Learning From Highly Confident Samples for Automatic Knee Osteoarthritis Severity Assessment: Data From the Osteoarthritis Initiative.
IEEE J. Biomed. Health Informatics, 2022
A Batch Bayesian Optimization Approach For Analog Circuit Synthesis Based On Multi-Points Selection Criterion.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
A Novel and Efficient Bayesian Optimization Approach for Analog Designs with Multi-Testbench.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2018
Smart-MSP: A Self-Adaptive Multiple Starting Point Optimization Approach for Analog Circuit Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
2017
Optimization and Quality Estimation of Circuit Design via Random Region Covering Method.
ACM Trans. Design Autom. Electr. Syst., 2017
2015
Automated Technology Migration Methodology for Mixed-Signal Circuit Based on Multistart Optimization Framework.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
2013
Mixed-signal system verification by SystemC/SystemC-AMS and HSIM-VCS in near field communication tag design.
Proceedings of the IEEE 10th International Conference on ASIC, 2013