Zhaojun Wo

According to our database1, Zhaojun Wo authored at least 5 papers in 2005.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of two.

Timeline

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Links

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Bibliography

2005
Technology Mapping for Reliability Enhancement in Logic Synthesis.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Yield-aware Floorplanning.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

An ILP Formulation for Yield-driven Architectural Synthesis.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Effective analytical delay model for transistor sizing.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Synthesis of Saturating Counters Using Traditional and Non-Traditional Basic Counters.
Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005


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