Zhao Zhang
Orcid: 0000-0002-9009-9045Affiliations:
- Chinese Academy of Sciences, Institute of Semiconductors, Beijing, China
According to our database1,
Zhao Zhang
authored at least 44 papers
between 2014 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
IEEE J. Solid State Circuits, February, 2024
A 32Gb/s NRZ Low-Bias DFB Driver with Frequency Boosting for High Efficiency Data Transmission.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
A 0.144 mm<sup>2</sup>12.5-16GHz PVT-Tolerant Dual-Path Offset-Charge-Pump-Based Fractional-N PLL Achieving 72.9 fSRMs Jitter, -271.5dB FoMN, and Sub-10% Jitter Variation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
2023
A 50Gb/s CMOS Optical Receiver With Si-Photonics PD for High-Speed Low-Latency Chiplet I/O.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2023
A 0.2-7.1-Gb/s Low-Jitter Full-Rate Reference-Less CDR for Communication Signal Analyzers.
IEEE Trans. Instrum. Meas., 2023
A 64-Gb/s Reference-Less PAM4 CDR with Asymmetrical Linear Phase Detector Soring 231.5-fsrms Clock Jitter and 0.21-pJ/bit Energy Efficiency in 40-nm CMOS.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A O.4V-VDD 2.25-to-2.75GHz ULV-SS-PLL Achieving 236.6fsrms Jitter, -253.8dB Jitter-Power FoM, and -76.1dBc Reference Spur.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 64-Gb/s 0.33-pJ/bit PAM4 Receiver Analog Front-End with a Single-Stage Triple-Peaking CTLE Achieving 22.5-dB Boost in 40-nm CMOS Process.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
A 0.0035-mm<sup>2</sup> 0.42-pJ/bit 8-32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased ChargeSharing Integrator, Alexander PFD, and 1-Tap DFE.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
A Wideband Low-Noise Linear LiDAR Analog Front-End Achieving 1.6 GHz Bandwidth, $\boldsymbol{2.7}\ \mathbf{pA}/\mathbf{Hz}^{\boldsymbol{0.5}}$ Input Referred Noise, and 103 $\mathbf{dB}\mathbf{\Omega}$ Transimpedance Gain.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
A $\boldsymbol{4} \times \boldsymbol{112}-\mathbf{Gb}/\mathbf{s}$ PAM-4 Silicon-Photonic Transceiver Front-End for Linear-Drive Co-Packaged Optics.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
A 12.75-to-16-GHz Spur-Jitter-Joint-Optimization SS-PLL Achieving -94.55-dBc Reference Spur, 31.9-fs Integrated Jitter and -260.1-dB FoM.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2022
A 56-Gb/s Reconfigurable Silicon-Photonics Transmitter Using High-Swing Distributed Driver and 2-Tap In-Segment Feed-Forward Equalizer in 65-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Design of a PAM-4 VCSEL-Based Transceiver Front-End for Beyond-400G Short-Reach Optical Interconnects.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR.
IEEE J. Solid State Circuits, 2022
A 224-Gb/s Inverter-Based TIA with Interleaved Active-Feedback and Distributed Peaking in 28-nm CMOS for Silicon Photonic Receivers.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022
A 0.006-mm<sup>2</sup>6-to-20-Gb/s NRZ Bang-Bang Clock and Data Recovery Circuit With Dual-Path Loop.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
A 0.004-mm<sup>2</sup> O.7-V 31.654-μW BPSK Demodulator Incorporating Dual-Path Loop Self-Biased PLL.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
A 50-Gb/s NRZ Receiver Targeting Low-Latency Multi-Chip Module Optical I/O in 45-nm SOI CMOS.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
2021
IEEE Open J. Circuits Syst., 2021
A 0.25-0.4-V, Sub-0.11-mW/GHz, 0.15-1.6-GHz PLL Using an Offset Dual-Path Architecture With Dynamic Charge Pumps.
IEEE J. Solid State Circuits, 2021
A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM4 Receiver with a -8-dB JTRAN 40-MHz 0.2-UIPP JTOL Clock and Data Recovery.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
A 50Gb/s High-Efficiency Si-Photonic Transmitter With Lump-Segmented MZM and Integrated PAM4 CDR.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2020
A 15-Gb/s 0.0037-mm² 0.019-pJ/Bit Full-Rate Programmable Multi-Pattern Pseudo-Random Binary Sequence Generator.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
A 0.65-V 12-16-GHz Sub-Sampling PLL With 56.4-fs<sub>rms</sub> Integrated Jitter and -256.4-dB FoM.
IEEE J. Solid State Circuits, 2020
A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Self-Biased PLL-Based Multiphase Clock Generator.
IEEE J. Solid State Circuits, 2020
2019
An 18-23 GHz 57.4-fs RMS Jitter -253.5-dB FoM Sub-Harmonically Injection-Locked All-Digital PLL With Single-Ended Injection Technique and ILFD Aided Adaptive Injection Timing Alignment Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
0.1-5 GHz wideband ΔΣ fractional-N frequency synthesiser for software-defined radio application.
IET Circuits Devices Syst., 2019
Single event upset failure probability evaluation and periodic scrubbing techniques for hierarchical parallel vision processors.
IEICE Electron. Express, 2019
A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase locked loop with fine frequency tuning circuits.
Sci. China Inf. Sci., 2019
A 0.25-0.4V, Sub-0.11mW/GHz, 0.15-1.6GHz PLL Using an Offset Dual-Path Loop Architecture with Dynamic Charge Pumps.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A 0.65V 12-to-16GHz Sub-Sampling PLL with 56.4fsrms Integrated Jitter and -256.4dB FoM.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Low-Power Multiphase Clock Generator.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
A 0.9-2.25-GHz Sub-0.2-mW/GHz Compact Low-Voltage Low-Power Hybrid Digital PLL With Loop Bandwidth-Tracking Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2018
A Fast Auto-Frequency Calibration Technique for Wideband PLL with Wide Reference Frequency Range.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
A 2.4-3.6-GHz Wideband Subharmonically Injection-Locked PLL With Adaptive Injection Timing Alignment Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2017
A 1.25-to-6.25 GHz -237.2-dB FOM wideband self-biased PLL for multi-rate serial link data transmitter.
IEICE Electron. Express, 2017
Sci. China Inf. Sci., 2017
A 18-to-23 GHz -253.5dB-FoM sub-harmonically injection-locked ADPLL with ILFD aided adaptive injection timing alignment technique.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2014
A novel 2.4-to-3.6 GHz wideband subharmonically injection-locked PLL with adaptively-aligned injection timing.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014