Zhanping Chen

According to our database, Zhanping Chen authored at least 27 papers between 1997 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

A High Output Power 1V Charge Pump and Power Switch for Configurable, In-Field-Programmable Metal eFuse on Intel 4 Logic Technology.

Stafford Hutchins, Jiabo Li, Atresh Sanne, Zhanping Chen, Mohammad M. Hasan, Uddalak Bhattacharya, Eric Karl, Jaydeep P. Kulkarni

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2017

A 0.9-μm² 1T1R Bit Cell in 14-nm High-Density Metal Fuse Technology for High-Volume Manufacturing and In-Field Programming.

Zhanping Chen, Sarvesh H. Kulkarni, Vincent E. Dorgan, Salil Manohar Rajarshi, Lei Jiang, Uddalak Bhattacharya

IEEE J. Solid State Circuits, 2017

2016

A High-Density Metal-Fuse Technology Featuring a 1.6 V Programmable Low-Voltage Bit Cell With Integrated 1 V Charge Pumps in 22 nm Tri-Gate CMOS.

Sarvesh H. Kulkarni, Zhanping Chen, Balaji Srinivasan, Brian Pedersen, Uddalak Bhattacharya, Kevin Zhang

IEEE J. Solid State Circuits, 2016

A 0.9um² 1T1R bit cell in 14nm SoC process for metal-fuse OTP array with hierarchical bitline, bit level redundancy, and power gating.

Zhanping Chen, Sarvesh H. Kulkarni, Vincent E. Dorgan, Uddalak Bhattacharya, Kevin Zhang

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2015

Low-voltage metal-fuse technology featuring a 1.6V-programmable 1T1R bit cell with an integrated 1V charge pump in 22nm tri-gate process.

Sarvesh H. Kulkarni, Zhanping Chen, Balaji Srinivasan, Brian Pedersen, Uddalak Bhattacharya, Kevin Zhang

Proceedings of the Symposium on VLSI Circuits, 2015

2010

A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 μ m ² <i>1T1R</i> Bit Cell in 32 nm High-k Metal-Gate CMOS.

Sarvesh H. Kulkarni, Zhanping Chen, Jun He, Lei Jiang, Brian Pedersen, Kevin Zhang

IEEE J. Solid State Circuits, 2010

2009

A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology.

Fatih Hamzaoglu, Kevin Zhang, Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Yong-Gee Ng, Andrei Pavlov, Ken Smits, Mark Bohr

IEEE J. Solid State Circuits, 2009

2008

A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications.

Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Tom Coan, Fatih Hamzaoglu, Walid M. Hafez, Chia-Hong Jan, Pramod Kolar, Sarvesh H. Kulkarni, Jie-Feng Lin, Yong-Gee Ng, Ian Post, Liqiong Wei, Ying Zhang, Kevin Zhang, Mark Bohr

IEEE J. Solid State Circuits, 2008

A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-Κ Metal-Gate CMOS Technology.

Fatih Hamzaoglu, Kevin Zhang, Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Yong-Gee Ng, Andrei Pavlov, Ken Smits, Mark Bohr

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2006

A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply.

Kevin Zhang, Uddalak Bhattacharya, Zhanping Chen, Fatih Hamzaoglu, Daniel Murray, Narendra Vallepalli, Yih Wang, Bo Zheng, Mark Bohr

IEEE J. Solid State Circuits, 2006

2005

SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction.

Kevin Zhang, Uddalak Bhattacharya, Zhanping Chen, Fatih Hamzaoglu, Daniel Murray, Narendra Vallepalli, Yih Wang, Bo Zheng, Mark Bohr

IEEE J. Solid State Circuits, 2005

2002

Vertically integrated SOI circuits for low-power and high-performance applications.

Liqiong Wei, Rongtian Zhang, Kaushik Roy, Zhanping Chen, David B. Janes

IEEE Trans. Very Large Scale Integr. Syst., 2002

IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions.

Zhanping Chen, Liqiong Wei, Ali Keshavarzi, Kaushik Roy

IEEE Des. Test Comput., 2002

2001

On effective I_DDQ testing of low-voltage CMOS circuits using leakage control techniques.

Zhanping Chen, Liqiong Wei, Kaushik Roy

IEEE Trans. Very Large Scale Integr. Syst., 2001

Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors.

James W. Tschanz, Siva G. Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

2000

Estimation of power dissipation using a novel power macromodelingtechnique.

Zhanping Chen, Kaushik Roy, Edwin K. P. Chong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques.

Zhanping Chen, Liqiong Wei, Kaushik Roy

Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

1999

Design and optimization of dual-threshold circuits for low-voltage low-power applications.

Liqiong Wei, Zhanping Chen, Kaushik Roy, Mark C. Johnson, Yibin Ye, Vivek De

IEEE Trans. Very Large Scale Integr. Syst., 1999

Multiple-Vdd multiple-Vth CMOS (MVCMOS) for low power applications.

Kaushik Roy, Liqiong Wei, Zhanping Chen

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Mixed-<i>V_th</i> (MVT) CMOS Circuit Design Methodology for Low Power Applications.

Liqiong Wei, Zhanping Chen, Kaushik Roy, Yibin Ye, Vivek De

Proceedings of the 36th Conference on Design Automation, 1999

1998

Efficient statistical approach to estimate power considering uncertain properties of primary inputs.

Zhanping Chen, Kaushik Roy, Tan-Li Chou

IEEE Trans. Very Large Scale Integr. Syst., 1998

Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks.

Zhanping Chen, Mark Johnson, Liqiong Wei, Kaushik Roy

Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Estimation of power sensitivity in sequential circuits with power macromodeling application.

Zhanping Chen, Kaushik Roy, Edwin K. P. Chong

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits.

Liqiong Wei, Zhanping Chen, Mark Johnson, Kaushik Roy, Vivek De

Proceedings of the 35th Conference on Design Automation, 1998

A Power Macromodeling Technique Based on Power Sensitivity.

Zhanping Chen, Kaushik Roy

Proceedings of the 35th Conference on Design Automation, 1998

Estimation of average switching power under accurate modeling of signal correlations.

Zhanping Chen, Kaushik Roy, Yibin Ye

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

1997

Power sensitivity - a new method to estimate power dissipation considering uncertain specifications of primary inputs.

Zhanping Chen, Kaushik Roy, Tan-Li Chou

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997