Zhangcai Huang

According to our database1, Zhangcai Huang authored at least 27 papers between 2005 and 2014.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2014
An Effective Model of the Overshooting Effect for Multiple-Input Gates in Nanometer Technologies.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

2013
An analytical model of the overshooting effect for multiple-input gates in nanometer technologies.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
Modeling the Overshooting Effect of Multi-Input gate in Nanometer Technologies.
J. Circuits Syst. Comput., 2012

A retargeting methodology of nano-watt CMOS reference circuit based on advanced compact MOSFET model.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load Effect.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

A sub-100nA power management system for wireless structure health monitoring applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Memristor Model for SPICE.
IEICE Trans. Electron., 2010

A low voltage CMOS rectifier for wirelessly powered devices.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A CMOS Sub-l-V nanopower current and voltage reference with leakage compensation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

A Highly Linear and Wide Input Range Four-Quadrant CMOS Analog Multiplier Using Active Feedback.
IEICE Trans. Electron., 2009

2007
An Effective SPICE3 Implementation of the Compound Element Pseudo-Transient Algorithm.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

A Low-Power Sub-1-V Low-Voltage Reference Using Body Effect.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Behavioral Circuit Macromodeling and Analog LSI Implementation for Automobile Engine Intake System.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
An Effective Pseudo-Transient Algorithm for Finding Dc Solutions of Nonlinear Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Determination of Interconnect Structural Parameters for Best- and Worst-Case Delays.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

An effective pseudo-transient algorithm for finding DC operating points of nonlinear circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Behavioral macromodeling of analog LSI implementation for automobile intake system.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A Wide Dynamic Range Four-Quadrant CMOS Analog Multiplier Using Active Feedback.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Effective capacitance for gate delay with RC loads.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005


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